Completion Detection Model for a Digital Comparator

Completion Detection Model for a Digital Comparator

The process of switching in a multi-bit magnitude comparator has been analyzed as well as the latency with which the output features are formed. A critical analysis of the possible methods for logic gate latency evaluation is presented, namely dual-rail signal disjunction, Muller C-element and NULL Convention Logic (NCL). A new economical logic circuit for realization of completion detection when performing the operation comparison has been proposed in connection with the conclusions made. The synthesized logic circuit is based on the parallelism in the comparator circuit. The signal generated by the aforementioned circuit enables the comparator to function under the conditions of asynchronous control.