����JFIFXX�����    $.' ",#(7),01444'9=82<.342  2!!22222222222222222222222222222222222222222222222222����"��4�� ���,�PG"Z_�4�˷����kjز�Z�,F+��_z�,�© �����zh6�٨�ic�fu���#ډb���_�N�?��wQ���5-�~�I���8����TK<5o�Iv-�����k�_U_�����~b�M��d����Ӝ�U�Hh��?]��E�w��Q���k�{��_}qFW7HTՑ��Y��F�?_�'ϔ��_�Ջt��=||I ��6�έ"�����D���/[�k�9���Y�8ds|\���Ҿp6�Ҵ���]��.����6�z<�v��@]�i%��$j��~�g��J>��no����pM[me�i$[����s�o�ᘨ�˸ nɜG-�ĨU�ycP�3.DB�li�;��hj���x7Z^�N�h������N3u{�:j�x�힞��#M&��jL P@_���� P��&��o8������9�����@Sz6�t7#O�ߋ �s}Yf�T���lmr����Z)'N��k�۞p����w\�Tȯ?�8`�O��i{wﭹW�[�r�� ��Q4F�׊���3m&L�=��h3����z~��#�\�l :�F,j@�� ʱ�wQT����8�"kJO���6�֚l����}���R�>ډK���]��y����&����p�}b��;N�1�m�r$�|��7�>e�@B�TM*-iH��g�D�)� E�m�|�ؘbҗ�a��Ҿ����t4���o���G��*oCN�rP���Q��@z,|?W[0�����:�n,jWiE��W��$~/�hp\��?��{(�0���+�Y8rΟ�+����>S-S����VN;�}�s?.����� w�9��˟<���Mq4�Wv'��{)0�1mB��V����W[�����8�/<� �%���wT^�5���b��)iM� pg�N�&ݝ��VO~�q���u���9� ����!��J27����$O-���! �:�%H��� ـ����y�ΠM=t{!S�� oK8������t<����è:a������[�����ա�H���~��w��Qz`�po�^ ����Q��n� �,uu�C�$ ^���,������8�#��:�6��e�|~���!�3�3.�\0��q��o�4`.|� ����y�Q�`~;�d�ׯ,��O�Zw�������`73�v�܋�<���Ȏ�� ـ4k��5�K�a�u�=9Yd��$>x�A�&�� j0� ���vF��� Y�|�y��� ~�6�@c��1vOp�Ig����4��l�OD���L����� R���c���j�_�uX6��3?nk��Wy�f;^*B� ��@�~a�`��Eu������+���6�L��.ü>��}y���}_�O�6�͐�:�YrG�X��kG�����l^w���~㒶sy��Iu�!� W ��X��N�7BV��O��!X�2����wvG�R�f�T#�����t�/?���%8�^�W�aT��G�cL�M���I��(J����1~�8�?aT ���]����AS�E��(��*E}� 2��#I/�׍qz��^t�̔���b�Yz4x���t�){ OH��+(E��A&�N�������XT��o��"�XC��'���)}�J�z�p� ��~5�}�^����+�6����w��c��Q�|Lp�d�H��}�(�.|����k��c4^�"�����Z?ȕ ��a<�L�!039C� �Eu�C�F�Ew�ç ;�n?�*o���B�8�bʝ���'#Rqf���M}7����]����s2tcS{�\icTx;�\��7K���P���ʇ Z O-��~��c>"��?�������P��E��O�8��@�8��G��Q�g�a�Վ���󁶠�䧘��_%#r�>�1�z�a��eb��qcPѵ��n���#L��� =��׀t� L�7�`��V���A{�C:�g���e@�w1 Xp3�c3�ġ����p��M"'-�@n4���fG��B3�DJ�8[Jo�ߐ���gK)ƛ��$���� ���8�3�����+���� �����6�ʻ���� ���S�kI�*KZlT _`���?��K����QK�d����B`�s}�>���`��*�>��,*@J�d�oF*����弝��O}�k��s��]��y�ߘ��c1G�V���<=�7��7����6�q�PT��tXԀ�!9*4�4Tހ3XΛex�46���Y��D ����� �BdemDa����\�_l,��G�/���֌7���Y�](�xTt^%�GE�����4�}bT���ڹ�����;Y)���B�Q��u��>J/J �⮶.�XԄ��j�ݳ�+E��d ��r�5�_D�1 ��o�� �B�x�΢�#���<��W�����8���R6�@g�M�.��� dr�D��>(otU��@x=��~v���2� ӣ�d�oBd��3�eO�6�㣷�����ݜ6��6Y��Qz`��S��{���\P�~z m5{J/L��1������<�e�ͅPu�b�]�ϔ���'������f�b� Zpw��c`"��i���BD@:)ִ�:�]��hv�E�w���T�l��P���"Ju�}��وV J��G6��. J/�Qgl߭�e�����@�z�Zev2u�)]կ�����7x���s�M�-<ɯ�c��r�v�����@��$�ޮ}lk���a���'����>x��O\�ZFu>�����ck#��&:��`�$�ai�>2Δ����l���oF[h��lE�ܺ�Πk:)���`�� $[6�����9�����kOw�\|���8}������ބ:��񶐕��I�A1/�=�2[�,�!��.}gN#�u����b��� ~��݊��}34q����d�E��Lc��$��"�[q�U�硬g^��%B �z���r�pJ�ru%v\h1Y�ne`ǥ:g���pQM~�^�Xi� ��`S�:V29.�P���V�?B�k�� AEvw%�_�9C�Q����wKekPؠ�\�;Io d�{ ߞo�c1eP����\� `����E=���@K<�Y���eڼ�J���w����{av�F�'�M�@/J��+9p���|]�����Iw &`��8���&M�hg��[�{��Xj��%��Ӓ�$��(����ʹN���<>�I���RY���K2�NPlL�ɀ)��&e����B+ь����( � �JTx���_?EZ� }@ 6�U���뙢ط�z��dWI�n` D����噥�[��uV��"�G&Ú����2g�}&m��?ċ�"����Om#��������� ��{�ON��"S�X��Ne��ysQ���@Fn��Vg���dX�~nj�]J�<�K]:��FW��b�������62�=��5f����JKw��bf�X�55��~J �%^����:�-�QIE��P��v�nZum� z � ~ə ���� ���ة����;�f��\v���g�8�1��f24;�V���ǔ�)����9���1\��c��v�/'Ƞ�w�������$�4�R-��t���� e�6�/�ġ �̕Ecy�J���u�B���<�W�ַ~�w[B1L۲�-JS΂�{���΃������A��20�c#��@ 0!1@AP"#2Q`$3V�%45a6�FRUq��� ����^7ׅ,$n�������+��F�`��2X'��0vM��p�L=������5��8������u�p~���.�`r�����\���O��,ư�0oS ��_�M�����l���4�kv\JSd���x���SW�<��Ae�IX����������$I���w�:S���y���›R��9�Q[���,�5�;�@]�%���u�@ *ro�lbI �� ��+���%m:�͇ZV�����u�̉����θau<�fc�.����{�4Ա� �Q����*�Sm��8\ujqs]{kN���)qO�y�_*dJ�b�7���yQqI&9�ԌK!�M}�R�;������S�T���1���i[U�ɵz�]��U)V�S6���3$K{�ߊ<�(� E]Զ[ǼENg�����'�\?#)Dkf��J���o��v���'�%ƞ�&K�u�!��b�35LX�Ϸ��63$K�a�;�9>,R��W��3�3� d�JeTYE.Mϧ��-�o�j3+y��y^�c�������VO�9NV\nd�1 ��!͕_)a�v;����թ�M�lWR1��)El��P;��yوÏ�u 3�k�5Pr6<�⒲l�!˞*��u־�n�!�l:����UNW ��%��Chx8vL'��X�@��*��)���̮��ˍ��� ���D-M�+J�U�kvK����+�x8��cY������?�Ԡ��~3mo��|�u@[XeY�C�\Kp�x8�oC�C�&����N�~3-H���� ��MX�s�u<`���~"WL��$8ξ��3���a�)|:@�m�\���^�`�@ҷ)�5p+��6���p�%i)P M���ngc�����#0Aruz���RL+xSS?���ʮ}()#�t��mˇ!��0}}y����<�e� �-ή�Ԩ��X������ MF���ԙ~l L.3���}�V뽺�v�����멬��Nl�)�2����^�Iq��a��M��qG��T�����c3#������3U�Ǎ���}��לS�|qa��ڃ�+���-��2�f����/��bz��ڐ�� �ݼ[2�ç����k�X�2�* �Z�d���J�G����M*9W���s{��w���T��x��y,�in�O�v��]���n����P�$�JB@=4�OTI�n��e�22a\����q�d���%�$��(���:���: /*�K[PR�fr\nڙdN���F�n�$�4�[�� U�zƶ����� �mʋ���,�ao�u 3�z� �x��Kn����\[��VFmbE;�_U��&V�Gg�]L�۪&#n%�$ɯ�dG���D�TI=�%+AB�Ru#��b4�1�»x�cs�YzڙJG��f��Il��d�eF'T� iA��T���uC�$����Y��H?����[!G`}���ͪ� �纤Hv\������j�Ex�K���!���OiƸ�Yj�+u-<���'q����uN�*�r\��+�]���<�wOZ.fp�ێ��,-*)V?j-kÊ#�`�r��dV����(�ݽBk�����G�ƛk�QmUڗe��Z���f}|����8�8��a���i��3'J�����~G_�^���d�8w������ R�`(�~�.��u���l�s+g�bv���W���lGc}��u���afE~1�Ue������Z�0�8�=e�� f@/�jqEKQQ�J��oN��J���W5~M>$6�Lt�;$ʳ{���^��6�{����v6���ķܰg�V�cnn �~z�x�«�,2�u�?cE+Ș�H؎�%�Za�)���X>uW�Tz�Nyo����s���FQƤ��$��*�&�LLXL)�1�" L��eO��ɟ�9=���:t��Z���c��Ž���Y?�ӭV�wv�~,Y��r�ۗ�|�y��GaF�����C�����.�+� ���v1���fήJ�����]�S��T��B��n5sW}y�$��~z�'�c ��8 ��� ,! �p��VN�S��N�N�q��y8z˱�A��4��*��'������2n<�s���^ǧ˭P�Jޮɏ�U�G�L�J�*#��<�V��t7�8����TĜ>��i}K%,���)[��z�21z ?�N�i�n1?T�I�R#��m-�����������������1����lA�`��fT5+��ܐ�c�q՝��ʐ��,���3�f2U�եmab��#ŠdQ�y>\��)�SLY����w#��.���ʑ�f��� ,"+�w�~�N�'�c�O�3F�������N<���)j��&��,-� �љ���֊�_�zS���TǦ����w�>��?�������n��U仆�V���e�����0���$�C�d���rP �m�׈e�Xm�Vu� �L��.�bֹ��� �[Դaզ���*��\y�8�Է:�Ez\�0�Kq�C b��̘��cө���Q��=0Y��s�N��S.���3.���O�o:���#���v7�[#߫ ��5�܎�L���Er4���9n��COWlG�^��0k�%<���ZB���aB_���������'=��{i�v�l�$�uC���mƎҝ{�c㱼�y]���W�i ��ߧc��m�H� m�"�"�����;Y�ߝ�Z�Ǔ�����:S#��|}�y�,/k�Ld� TA�(�AI$+I3��;Y*���Z��}|��ӧO��d�v��..#:n��f>�>���ȶI�TX��� 8��y����"d�R�|�)0���=���n4��6ⲑ�+��r<�O�܂~zh�z����7ܓ�HH�Ga롏���nCo�>������a ���~]���R���̲c?�6(�q�;5%� |�uj�~z8R=X��I�V=�|{v�Gj\gc��q����z�؋%M�ߍ����1y��#��@f^���^�>N�����#x#۹��6�Y~�?�dfPO��{��P�4��V��u1E1J �*|���%���JN��`eWu�zk M6���q t[�� ��g�G���v��WIG��u_ft����5�j�"�Y�:T��ɐ���*�;� e5���4����q$C��2d�}���� _S�L#m�Yp��O�.�C�;��c����Hi#֩%+) �Ӎ��ƲV���SYź��g |���tj��3�8���r|���V��1#;.SQ�A[���S������#���`n�+���$��$I �P\[�@�s��(�ED�z���P��])8�G#��0B��[ى��X�II�q<��9�~[Z멜�Z�⊔IWU&A>�P~�#��dp<�?����7���c��'~���5 ��+$���lx@�M�dm��n<=e�dyX��?{�|Aef ,|n3�<~z�ƃ�uۧ�����P��Y,�ӥQ�*g�#먙R�\���;T��i,��[9Qi歉����c>]9�� ��"�c��P�� �Md?٥��If�ت�u��k��/����F��9�c*9��Ǎ:�ØF���z�n*�@|I�ށ9����N3{'��[�'ͬ�Ҳ4��#}��!�V� Fu��,�,mTIk���v C�7v���B�6k�T9��1�*l� '~��ƞF��lU��'�M ����][ΩũJ_�{�i�I�n��$���L�� j��O�dx�����kza۪��#�E��Cl����x˘�o�����V���ɞ�ljr��)�/,�߬h�L��#��^��L�ф�,íMƁe�̩�NB�L�����iL����q�}��(��q��6IçJ$�W�E$��:������=#����(�K�B����zђ <��K(�N�۫K�w��^O{!����)�H���>x�������lx�?>Պ�+�>�W���,Ly!_�D���Ō�l���Q�!�[ �S����J��1��Ɛ�Y}��b,+�Lo�x�ɓ)����=�y�oh�@�꥟/��I��ѭ=��P�y9��� �ۍYӘ�e+�p�Jnϱ?V\SO%�(�t� ���=?MR�[Ș�����d�/ ��n�l��B�7j� ��!�;ӥ�/�[-���A�>�dN�sLj ��,ɪv��=1c�.SQ�O3�U���ƀ�ܽ�E����������̻��9G�ϷD�7(�}��Ävӌ\�y�_0[w ���<΍>����a_��[0+�L��F.�޺��f�>oN�T����q;���y\��bՃ��y�jH�<|q-eɏ�_?_9+P���Hp$�����[ux�K w�Mw��N�ی'$Y2�=��q���KB��P��~������Yul:�[<����F1�2�O���5=d����]Y�sw:���Ϯ���E��j,_Q��X��z`H1,#II ��d�wr��P˂@�ZJV����y$�\y�{}��^~���[:N����ߌ�U�������O��d�����ؾe��${p>G��3c���Ė�lʌ�� ת��[��`ϱ�-W����dg�I��ig2��� ��}s ��ؤ(%#sS@���~���3�X�nRG�~\jc3�v��ӍL��M[JB�T��s3}��j�Nʖ��W����;7��ç?=X�F=-�=����q�ߚ���#���='�c��7���ڑW�I(O+=:uxq�������������e2�zi+�kuG�R��������0�&e�n���iT^J����~\jy���p'dtG��s����O��3����9* �b#Ɋ�� p������[Bws�T�>d4�ۧs���nv�n���U���_�~,�v����ƜJ1��s�� �QIz��)�(lv8M���U=�;����56��G���s#�K���MP�=��LvyGd��}�VwWBF�'�à �?MH�U�g2�� ����!�p�7Q��j��ڴ����=��j�u��� Jn�A s���uM������e��Ɔ�Ҕ�!)'��8Ϣ�ٔ��ޝ(��Vp���צ֖d=�IC�J�Ǡ{q������kԭ�߸���i��@K����u�|�p=..�*+����x�����z[Aqġ#s2a�Ɗ���RR�)*HRsi�~�a &f��M��P����-K�L@��Z��Xy�'x�{}��Zm+���:�)�) IJ�-i�u���� ���ܒH��'�L(7�y�GӜq���� j��� 6ߌg1�g�o���,kر���tY�?W,���p���e���f�OQS��!K�۟cҒA�|ս�j�>��=⬒��˧L[�� �߿2JaB~R��u�:��Q�] �0H~���]�7��Ƽ�I���(}��cq '�ήET���q�?f�ab���ӥvr� �)o��-Q��_'����ᴎo��K������;��V���o��%���~OK ����*��b�f:���-ťIR��`B�5!RB@���ï�� �u �̯e\�_U�_������� g�ES��3�������QT��a����x����U<~�c?�*�#]�MW,[8O�a�x��]�1bC|踤�P��lw5V%�)�{t�<��d��5���0i�XSU��m:��Z�┵�i�"��1�^B�-��P�hJ��&)O��*�D��c�W��vM��)����}���P��ܗ-q����\mmζZ-l@�}��a��E�6��F�@��&Sg@���ݚ�M����� ȹ 4����#p�\H����dYDo�H���"��\��..R�B�H�z_�/5˘����6��KhJR��P�mƶi�m���3�,#c�co��q�a)*Pt����R�m�k�7x�D�E�\Y�閣_X�<���~�)���c[[�BP����6�Yq���S��0����%_����;��Àv�~�| VS؇ ��'O0��F0��\���U�-�d@�����7�SJ*z��3n��y��P����O���������m�~�P�3|Y��ʉr#�C�<�G~�.,! ���bqx���h~0=��!ǫ�jy����l�O,�[B��~��|9��ٱ����Xly�#�i�B��g%�S��������tˋ���e���ې��\[d�t)��.+u�|1 ������#�~Oj����hS�%��i.�~X���I�H�m��0n���c�1uE�q��cF�RF�o���7� �O�ꮧ� ���ۛ{��ʛi5�rw?׌#Qn�TW��~?y$��m\�\o����%W� ?=>S�N@�� �Ʈ���R����N�)�r"C�:��:����� �����#��qb��Y�. �6[��2K����2u�Ǧ�HYR��Q�MV��� �G�$��Q+.>�����nNH��q�^��� ����q��mM��V��D�+�-�#*�U�̒ ���p욳��u:�������IB���m���PV@O���r[b= �� ��1U�E��_Nm�yKbN�O���U�}�the�`�|6֮P>�\2�P�V���I�D�i�P�O;�9�r�mAHG�W�S]��J*�_�G��+kP�2����Ka�Z���H�'K�x�W�MZ%�O�YD�Rc+o��?�q��Ghm��d�S�oh�\�D�|:W������UA�Qc yT�q������~^�H��/��#p�CZ���T�I�1�ӏT����4��"�ČZ�����}��`w�#�*,ʹ�� ��0�i��課�Om�*�da��^gJ݅{���l�e9uF#T�ֲ��̲�ٞC"�q���ߍ ոޑ�o#�XZTp����@ o�8��(jd��xw�]�,f���`~�|,s��^����f�1���t��|��m�򸄭/ctr��5s��7�9Q�4�H1꠲BB@l9@���C�����+�wp�xu�£Yc�9��?`@#�o�mH�s2��)�=��2�.�l����jg�9$�Y�S�%*L������R�Y������7Z���,*=�䷘$�������arm�o�ϰ���UW.|�r�uf����IGw�t����Zwo��~5 ��YյhO+=8fF�)�W�7�L9lM�̘·Y���֘YLf�큹�pRF���99.A �"wz��=E\Z���'a� 2��Ǚ�#;�'}�G���*��l��^"q��+2FQ� hj��kŦ��${���ޮ-�T�٭cf�|�3#~�RJ����t��$b�(R��(����r���dx� >U b�&9,>���%E\� Ά�e�$��'�q't��*�א���ެ�b��-|d���SB�O�O��$�R+�H�)�܎�K��1m`;�J�2�Y~9��O�g8=vqD`K[�F)k�[���1m޼c��n���]s�k�z$@��)!I �x՝"v��9=�ZA=`Ɠi �:�E��)`7��vI��}d�YI�_ �o�:ob���o ���3Q��&D&�2=�� �Ά��;>�h����y.*ⅥS������Ӭ�+q&����j|UƧ����}���J0��WW< ۋS�)jQR�j���Ư��rN)�Gű�4Ѷ(�S)Ǣ�8��i��W52���No˓� ۍ%�5brOn�L�;�n��\G����=�^U�dI���8$�&���h��'���+�(������cȁ߫k�l��S^���cƗjԌE�ꭔ��gF���Ȓ��@���}O���*;e�v�WV���YJ\�]X'5��ղ�k�F��b 6R�o՜m��i N�i����>J����?��lPm�U��}>_Z&�KK��q�r��I�D�Չ~�q�3fL�:S�e>���E���-G���{L�6p�e,8��������QI��h��a�Xa��U�A'���ʂ���s�+טIjP�-��y�8ۈZ?J$��W�P� ��R�s�]��|�l(�ԓ��sƊi��o(��S0��Y� 8�T97.�����WiL��c�~�dxc�E|�2!�X�K�Ƙਫ਼�$((�6�~|d9u+�qd�^3�89��Y�6L�.I�����?���iI�q���9�)O/뚅����O���X��X�V��ZF[�یgQ�L��K1���RҖr@v�#��X�l��F���Нy�S�8�7�kF!A��sM���^rkp�jP�DyS$N���q��nxҍ!U�f�!eh�i�2�m���`�Y�I�9r�6� �TF���C}/�y�^���Η���5d�'��9A-��J��>{�_l+�`��A���[�'��յ�ϛ#w:݅�%��X�}�&�PSt�Q�"�-��\縵�/����$Ɨh�Xb�*�y��BS����;W�ջ_mc�����vt?2}1�;qS�d�d~u:2k5�2�R�~�z+|HE!)�Ǟl��7`��0�<�,�2*���Hl-��x�^����'_TV�gZA�'j� ^�2Ϊ��N7t�����?w�� �x1��f��Iz�C-Ȗ��K�^q�;���-W�DvT�7��8�Z�������� hK�(P:��Q- �8�n�Z���܃e貾�<�1�YT<�,�����"�6{/ �?�͟��|1�:�#g��W�>$����d��J��d�B��=��jf[��%rE^��il:��B���x���Sּ�1հ��,�=��*�7 fcG��#q� �eh?��2�7�����,�!7x��6�n�LC�4x��},Geǝ�tC.��vS �F�43��zz\��;QYC,6����~;RYS/6���|2���5���v��T��i����������mlv��������&� �nRh^ejR�LG�f���? �ۉҬܦƩ��|��Ȱ����>3����!v��i�ʯ�>�v��オ�X3e���_1z�Kȗ\<������!�8���V��]��?b�k41�Re��T�q��mz��TiOʦ�Z��Xq���L������q"+���2ۨ��8}�&N7XU7Ap�d�X��~�׿��&4e�o�F��� �H����O���č�c�� 懴�6���͉��+)��v;j��ݷ�� �UV�� i��� j���Y9GdÒJ1��詞�����V?h��l����l�cGs�ځ�������y�Ac�����\V3�? �� ܙg�>qH�S,�E�W�[�㺨�uch�⍸�O�}���a��>�q�6�n6����N6�q������N ! 1AQaq�0@����"2BRb�#Pr���3C`��Scst���$4D���%Td�� ?���N����a��3��m���C���w��������xA�m�q�m���m������$����4n淿t'��C"w��zU=D�\R+w�p+Y�T�&�պ@��ƃ��3ޯ?�Aﶂ��aŘ���@-�����Q�=���9D��ռ�ѻ@��M�V��P��܅�G5�f�Y<�u=,EC)�<�Fy'�"�&�չ�X~f��l�KԆV��?�� �W�N����=(� �;���{�r����ٌ�Y���h{�١������jW����P���Tc�����X�K�r��}���w�R��%��?���E��m�� �Y�q|����\lEE4���r���}�lsI�Y������f�$�=�d�yO����p�����yBj8jU�o�/�S��?�U��*������ˍ�0������u�q�m [�?f����a�� )Q�>����6#������� ?����0UQ����,IX���(6ڵ[�DI�MNލ�c&���υ�j\��X�R|,4��� j������T�hA�e��^���d���b<����n�� �즇�=!���3�^�`j�h�ȓr��jẕ�c�,ٞX����-����a�ﶔ���#�$��]w�O��Ӫ�1y%��L�Y<�wg#�ǝ�̗`�x�xa�t�w��»1���o7o5��>�m뭛C���Uƃߜ}�C���y1Xνm�F8�jI���]����H���ۺиE@I�i;r�8ӭ����V�F�Շ| ��&?�3|x�B�MuS�Ge�=Ӕ�#BE5G�����Y!z��_e��q�р/W>|-�Ci߇�t�1ޯќd�R3�u��g�=0 5��[?�#͏��q�cf���H��{ ?u�=?�?ǯ���}Z��z���hmΔ�BFTW�����<�q�(v� ��!��z���iW]*�J�V�z��gX֧A�q�&��/w���u�gYӘa���; �i=����g:��?2�dž6�ى�k�4�>�Pxs����}������G�9��3 ���)gG�R<>r h�$��'nc�h�P��Bj��J�ҧH� -��N1���N��?��~��}-q!=��_2hc�M��l�vY%UE�@|�v����M2�.Y[|y�"Eï��K�ZF,�ɯ?,q�?v�M 80jx�"�;�9vk�����+ ֧�� �ȺU��?�%�vcV��mA�6��Qg^M����A}�3�nl� QRN�l8�kkn�'�����(��M�7m9و�q���%ޟ���*h$Zk"��$�9��: �?U8�Sl��,,|ɒ��xH(ѷ����Gn�/Q�4�P��G�%��Ա8�N��!� �&�7�;���eKM7�4��9R/%����l�c>�x;������>��C�:�����t��h?aKX�bhe�ᜋ^�$�Iհ �hr7%F$�E��Fd���t��5���+�(M6�t����Ü�UU|zW�=a�Ts�Tg������dqP�Q����b'�m���1{|Y����X�N��b �P~��F^F:����k6�"�j!�� �I�r�`��1&�-$�Bevk:y���#yw��I0��x��=D�4��tU���P�ZH��ڠ底taP��6����b>�xa����Q�#� WeF��ŮNj�p�J* mQ�N����*I�-*�ȩ�F�g�3 �5��V�ʊ�ɮ�a��5F���O@{���NX��?����H�]3��1�Ri_u��������ѕ�� ����0��� F��~��:60�p�͈�S��qX#a�5>���`�o&+�<2�D����: �������ڝ�$�nP���*)�N�|y�Ej�F�5ټ�e���ihy�Z �>���k�bH�a�v��h�-#���!�Po=@k̆IEN��@��}Ll?j�O������߭�ʞ���Q|A07x���wt!xf���I2?Z��<ץ�T���cU�j��]��陎Ltl �}5�ϓ��$�,��O�mˊ�;�@O��jE��j(�ا,��LX���LO���Ц�90�O �.����a��nA���7������j4 ��W��_ٓ���zW�jcB������y՗+EM�)d���N�g6�y1_x��p�$Lv:��9�"z��p���ʙ$��^��JԼ*�ϭ����o���=x�Lj�6�J��u82�A�H�3$�ٕ@�=Vv�]�'�qEz�;I˼��)��=��ɯ���x �/�W(V���p�����$ �m�������u�����񶤑Oqˎ�T����r��㠚x�sr�GC��byp�G��1ߠ�w e�8�$⿄����/�M{*}��W�]˷.�CK\�ުx���/$�WPw���r� |i���&�}�{�X� �>��$-��l���?-z���g����lΆ���(F���h�vS*���b���߲ڡn,|)mrH[���a�3�ר�[1��3o_�U�3�TC�$��(�=�)0�kgP���� ��u�^=��4 �WYCҸ:��vQ�ר�X�à��tk�m,�t*��^�,�}D*� �"(�I��9R����>`�`��[~Q]�#af��i6l��8���6�:,s�s�N6�j"�A4���IuQ��6E,�GnH��zS�HO�uk�5$�I�4��ؤ�Q9�@��C����wp�BGv[]�u�Ov���0I4���\��y�����Q�Ѹ��~>Z��8�T��a��q�ޣ;z��a���/��S��I:�ܫ_�|������>=Z����8:�S��U�I�J��"IY���8%b8���H��:�QO�6�;7�I�S��J��ҌAά3��>c���E+&jf$eC+�z�;��V����� �r���ʺ������my�e���aQ�f&��6�ND��.:��NT�vm�<- u���ǝ\MvZY�N�NT��-A�>jr!S��n�O 1�3�Ns�%�3D@���`������ܟ 1�^c<���� �a�ɽ�̲�Xë#�w�|y�cW�=�9I*H8�p�^(4���՗�k��arOcW�tO�\�ƍR��8����'�K���I�Q�����?5�>[�}��yU�ײ -h��=��% q�ThG�2�)���"ו3]�!kB��*p�FDl�A���,�eEi�H�f�Ps�����5�H:�Փ~�H�0Dت�D�I����h�F3�������c��2���E��9�H��5�zԑ�ʚ�i�X�=:m�xg�hd(�v����׊�9iS��O��d@0ڽ���:�p�5�h-��t�&���X�q�ӕ,��ie�|���7A�2���O%P��E��htj��Y1��w�Ѓ!����  ���� ࢽ��My�7�\�a�@�ţ�J �4�Ȼ�F�@o�̒?4�wx��)��]�P��~�����u�����5�����7X ��9��^ܩ�U;Iꭆ 5 �������eK2�7(�{|��Y׎ �V��\"���Z�1� Z�����}��(�Ǝ"�1S���_�vE30>���p;� ΝD��%x�W�?W?v����o�^V�i�d��r[��/&>�~`�9Wh��y�;���R��� ;;ɮT��?����r$�g1�K����A��C��c��K��l:�'��3 c�ﳯ*"t8�~l��)���m��+U,z��`(�>yJ�?����h>��]��v��ЍG*�{`��;y]��I�T� ;c��NU�fo¾h���/$���|NS���1�S�"�H��V���T���4��uhǜ�]�v;���5�͠x��'C\�SBpl���h}�N����� A�Bx���%��ޭ�l��/����T��w�ʽ]D�=����K���ž�r㻠l4�S�O?=�k �M:� ��c�C�a�#ha���)�ѐxc�s���gP�iG��{+���x���Q���I= �� z��ԫ+ �8"�k�ñ�j=|����c ��y��CF��/��*9ж�h{ �?4�o� ��k�m�Q�N�x��;�Y��4膚�a�w?�6�>e]�����Q�r�:����g�,i"�����ԩA�*M�<�G��b�if��l^M��5� �Ҩ�{����6J��ZJ�����P�*�����Y���ݛu�_4�9�I8�7���������,^ToR���m4�H��?�N�S�ѕw��/S��甍�@�9H�S�T��t�ƻ���ʒU��*{Xs�@����f�����֒Li�K{H�w^���������Ϥm�tq���s� ���ք��f:��o~s��g�r��ט� �S�ѱC�e]�x���a��) ���(b-$(�j>�7q�B?ӕ�F��hV25r[7 Y� }L�R��}����*sg+��x�r�2�U=�*'WS��ZDW]�WǞ�<��叓���{�$�9Ou4��y�90-�1�'*D`�c�^o?(�9��u���ݐ��'PI&� f�Jݮ�������:wS����jfP1F:X �H�9dԯ���˝[�_54 �}*;@�ܨ�� ð�yn�T���?�ןd�#���4rG�ͨ��H�1�|-#���Mr�S3��G�3�����)�.᧏3v�z֑��r����$G"�`j �1t��x0<Ɔ�Wh6�y�6��,œ�Ga��gA����y��b��)��h�D��ß�_�m��ü �gG;��e�v��ݝ�nQ� ��C����-�*��o���y�a��M��I�>�<���]obD��"�:���G�A��-\%LT�8���c�)��+y76���o�Q�#*{�(F�⽕�y����=���rW�\p���۩�c���A���^e6��K������ʐ�cVf5$�'->���ՉN"���F�"�UQ@�f��Gb~��#�&�M=��8�ט�JNu9��D��[̤�s�o�~������ G��9T�tW^g5y$b��Y'��س�Ǵ�=��U-2 #�MC�t(�i� �lj�@Q 5�̣i�*�O����s�x�K�f��}\��M{E�V�{�υ��Ƈ�����);�H����I��fe�Lȣr�2��>��W�I�Ȃ6������i��k�� �5�YOxȺ����>��Y�f5'��|��H+��98pj�n�.O�y�������jY��~��i�w'������l�;�s�2��Y��:'lg�ꥴ)o#'Sa�a�K��Z� �m��}�`169�n���"���x��I ��*+� }F<��cГ���F�P�������ֹ*�PqX�x۩��,� ��N�� �4<-����%����:��7����W���u�`����� $�?�I��&����o��o��`v�>��P��"��l���4��5'�Z�gE���8���?��[�X�7(��.Q�-��*���ތL@̲����v��.5���[��=�t\+�CNܛ��,g�SQnH����}*F�G16���&:�t��4ُ"A��̣��$�b �|����#rs��a�����T�� ]�<�j��BS�('$�ɻ� �wP;�/�n��?�ݜ��x�F��yUn�~mL*-�������Xf�wd^�a�}��f�,=t�׵i�.2/wpN�Ep8�OР���•��R�FJ� 55TZ��T �ɭ�<��]��/�0�r�@�f��V��V����Nz�G��^���7hZi����k��3�,kN�e|�vg�1{9]_i��X5y7� 8e]�U����'�-2,���e"����]ot�I��Y_��n�(JҼ��1�O ]bXc���Nu�No��pS���Q_���_�?i�~�x h5d'�(qw52] ��'ޤ�q��o1�R!���`ywy�A4u���h<קy���\[~�4�\ X�Wt/� 6�����n�F�a8��f���z �3$�t(���q��q�x��^�XWeN'p<-v�!�{�(>ӽDP7��ո0�y)�e$ٕv�Ih'Q�EA�m*�H��RI��=:��� ���4牢) �%_iN�ݧ�l]� �Nt���G��H�L��� ɱ�g<���1V�,�J~�ٹ�"K��Q�� 9�HS�9�?@��k����r�;we݁�]I�!{ �@�G�[�"��`���J:�n]�{�cA�E����V��ʆ���#��U9�6����j�#Y�m\��q�e4h�B�7��C�������d<�?J����1g:ٳ���=Y���D�p�ц� ׈ǔ��1�]26؜oS�'��9�V�FVu�P�h�9�xc�oq�X��p�o�5��Ա5$�9W�V(�[Ak�aY錎qf;�'�[�|���b�6�Ck��)��#a#a˙��8���=äh�4��2��C��4tm^ �n'c���]GQ$[Wҿ��i���vN�{Fu ��1�gx��1┷���N�m��{j-,��x�� Ūm�ЧS�[�s���Gna���䑴�� x�p 8<������97�Q���ϴ�v�aϚG��Rt�Һ׈�f^\r��WH�JU�7Z���y)�vg=����n��4�_)y��D'y�6�]�c�5̪�\� �PF�k����&�c;��cq�$~T�7j ���nç]�<�g ":�to�t}�159�<�/�8������m�b�K#g'I'.W�����6��I/��>v��\�MN��g���m�A�yQL�4u�Lj�j9��#44�t��l^�}L����n��R��!��t��±]��r��h6ٍ>�yҏ�N��fU�� ���� Fm@�8}�/u��jb9������he:A�y�ծw��GpΧh�5����l}�3p468��)U��d��c����;Us/�֔�YX�1�O2��uq�s��`hwg�r~�{ R��mhN��؎*q 42�*th��>�#���E����#��Hv�O����q�}�����6�e��\�,Wk�#���X��b>��p}�դ��3���T5��†��6��[��@�P�y*n��|'f�֧>�lư΂�̺����SU�'*�q�p�_S�����M�� '��c�6�����m�� ySʨ;M��r���Ƌ�m�Kxo,���Gm�P��A�G�:��i��w�9�}M(�^�V��$ǒ�ѽ�9���|���� �a����J�SQ�a���r�B;����}���ٻ֢�2�%U���c�#�g���N�a�ݕ�'�v�[�OY'��3L�3�;,p�]@�S��{ls��X�'���c�jw�k'a�.��}�}&�� �dP�*�bK=ɍ!����;3n�gΊU�ߴmt�'*{,=SzfD� A��ko~�G�aoq�_mi}#�m�������P�Xhύ����mxǍ�΂���巿zf��Q���c���|kc�����?���W��Y�$���_Lv����l߶��c���`?����l�j�ݲˏ!V��6����U�Ђ(A���4y)H���p�Z_�x��>���e��R��$�/�`^'3qˏ�-&Q�=?��CFVR �D�fV�9��{�8g�������n�h�(P"��6�[�D���< E�����~0<@�`�G�6����Hг�cc�� �c�K.5��D��d�B���`?�XQ��2��ٿyqo&+�1^� DW�0�ꊩ���G�#��Q�nL3��c���������/��x ��1�1[y�x�პCW��C�c�UĨ80�m�e�4.{�m��u���I=��f�����0QRls9���f���������9���~f�����Ǩ��a�"@�8���ȁ�Q����#c�ic������G��$���G���r/$W�(��W���V�"��m�7�[m�A�m����bo��D� j����۳� l���^�k�h׽����� ��#� iXn�v��eT�k�a�^Y�4�BN��ĕ��0 !01@Q"2AaPq3BR������?���@4�Q�����T3,���㺠�W�[=JK�Ϟ���2�r^7��vc�:�9 �E�ߴ�w�S#d���Ix��u��:��Hp��9E!�� V 2;73|F��9Y���*ʬ�F��D����u&���y؟��^EA��A��(ɩ���^��GV:ݜDy�`��Jr29ܾ�㝉��[���E;Fzx��YG��U�e�Y�C���� ����v-tx����I�sם�Ę�q��Eb�+P\ :>�i�C'�;�����k|z�رn�y]�#ǿb��Q��������w�����(�r|ӹs��[�D��2v-%��@;�8<a���[\o[ϧw��I!��*0�krs)�[�J9^��ʜ��p1)� "��/_>��o��<1����A�E�y^�C��`�x1'ܣn�p��s`l���fQ��):�l����b>�Me�jH^?�kl3(�z:���1ŠK&?Q�~�{�ٺ�h�y���/�[��V�|6��}�KbX����mn[-��7�5q�94�������dm���c^���h� X��5��<�eޘ>G���-�}�دB�ޟ� ��|�rt�M��V+�]�c?�-#ڛ��^ǂ}���Lkr���O��u�>�-D�ry� D?:ޞ�U��ǜ�7�V��?瓮�"�#���r��չģVR;�n���/_� ؉v�ݶe5d�b9��/O��009�G���5n�W����JpA�*�r9�>�1��.[t���s�F���nQ� V 77R�]�ɫ8����_0<՜�IF�u(v��4��F�k�3��E)��N:��yڮe��P�`�1}�$WS��J�SQ�N�j�ٺ��޵�#l���ј(�5=��5�lǏmoW�v-�1����v,W�mn��߀$x�<����v�j(����c]��@#��1������Ǔ���o'��u+����;G�#�޸��v-lη��/(`i⣍Pm^���ԯ̾9Z��F��������n��1��� ��]�[��)�'������:�֪�W��FC����� �B9،!?���]��V��A�Վ�M��b�w��G F>_DȬ0¤�#�QR�[V��kz���m�w�"��9ZG�7'[��=�Q����j8R?�zf�\a�=��O�U����*oB�A�|G���2�54 �p��.w7� �� ��&������ξxGHp� B%��$g�����t�Џ򤵍z���HN�u�Я�-�'4��0��;_��3 !01"@AQa2Pq#3BR������?��ʩca��en��^��8���<�u#��m*08r��y�N"�<�Ѳ0��@\�p��� �����Kv�D��J8�Fҽ� �f�Y��-m�ybX�NP����}�!*8t(�OqѢ��Q�wW�K��ZD��Δ^e��!� ��B�K��p~�����e*l}z#9ң�k���q#�Ft�o��S�R����-�w�!�S���Ӥß|M�l޶V��!eˈ�8Y���c�ЮM2��tk���� ������J�fS����Ö*i/2�����n]�k�\���|4yX�8��U�P.���Ы[���l��@"�t�<������5�lF���vU�����W��W��;�b�cД^6[#7@vU�xgZv��F�6��Q,K�v��� �+Ъ��n��Ǣ��Ft���8��0��c�@�!�Zq s�v�t�;#](B��-�nῃ~���3g������5�J�%���O������n�kB�ĺ�.r��+���#�N$?�q�/�s�6��p��a����a��J/��M�8��6�ܰ"�*������ɗud"\w���aT(����[��F��U՛����RT�b���n�*��6���O��SJ�.�ij<�v�MT��R\c��5l�sZB>F��<7�;EA��{��E���Ö��1U/�#��d1�a�n.1ě����0�ʾR�h��|�R��Ao�3�m3 ��%�� ���28Q� ��y��φ���H�To�7�lW>����#i`�q���c����a��� �m,B�-j����݋�'mR1Ήt�>��V��p���s�0IbI�C.���1R�ea�����]H�6����������4B>��o��](��$B���m�����a�!=��?�B� K�Ǿ+�Ծ"�n���K��*��+��[T#�{E�J�S����Q�����s�5�:�U�\wĐ�f�3����܆&�)����I���Ԇw��E T�lrTf6Q|R�h:��[K�� �z��c֧�G�C��%\��_�a�84��HcO�bi��ؖV��7H �)*ģK~Xhչ0��4?�0��� �E<���}3���#���u�?�� ��|g�S�6ꊤ�|�I#Hڛ� �ա��w�X��9��7���Ŀ%�SL��y6č��|�F�a 8���b��$�sק�h���b9RAu7�˨p�Č�_\*w��묦��F ����4D~�f����|(�"m���NK��i�S�>�$d7SlA��/�²����SL��|6N�}���S�˯���g��]6��; �#�.��<���q'Q�1|KQ$�����񛩶"�$r�b:���N8�w@��8$�� �AjfG|~�9F ���Y��ʺ��Bwؒ������M:I岎�G��`s�YV5����6��A �b:�W���G�q%l�����F��H���7�������Fsv7��k�� 403WebShell
403Webshell
Server IP : 104.21.45.146  /  Your IP : 172.70.80.14
Web Server : Apache/2.4.52 (Ubuntu)
System : Linux ip-172-31-19-221 6.8.0-1029-aws #31~22.04.1-Ubuntu SMP Thu Apr 24 21:16:18 UTC 2025 x86_64
User : www-data ( 33)
PHP Version : 8.1.28
Disable Function : NONE
MySQL : OFF  |  cURL : ON  |  WGET : ON  |  Perl : ON  |  Python : OFF  |  Sudo : ON  |  Pkexec : ON
Directory :  /usr/lib/modules/6.8.0-1029-aws/build/arch/mips/include/asm/mach-bcm63xx/

Upload File :
current_dir [ Writeable ] document_root [ Writeable ]

 

Command :


[ Back ]     

Current File : /usr/lib/modules/6.8.0-1029-aws/build/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef BCM63XX_CPU_H_
#define BCM63XX_CPU_H_

#include <linux/types.h>
#include <linux/init.h>

/*
 * Macro to fetch bcm63xx cpu id and revision, should be optimized at
 * compile time if only one CPU support is enabled (idea stolen from
 * arm mach-types)
 */
#define BCM3368_CPU_ID		0x3368
#define BCM6328_CPU_ID		0x6328
#define BCM6338_CPU_ID		0x6338
#define BCM6345_CPU_ID		0x6345
#define BCM6348_CPU_ID		0x6348
#define BCM6358_CPU_ID		0x6358
#define BCM6362_CPU_ID		0x6362
#define BCM6368_CPU_ID		0x6368

void __init bcm63xx_cpu_init(void);
u8 bcm63xx_get_cpu_rev(void);
unsigned int bcm63xx_get_cpu_freq(void);

static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id)
{
	switch (cpu_id) {
#ifdef CONFIG_BCM63XX_CPU_3368
		case BCM3368_CPU_ID:
#endif

#ifdef CONFIG_BCM63XX_CPU_6328
		case BCM6328_CPU_ID:
#endif

#ifdef CONFIG_BCM63XX_CPU_6338
		case BCM6338_CPU_ID:
#endif

#ifdef CONFIG_BCM63XX_CPU_6345
		case BCM6345_CPU_ID:
#endif

#ifdef CONFIG_BCM63XX_CPU_6348
		case BCM6348_CPU_ID:
#endif

#ifdef CONFIG_BCM63XX_CPU_6358
		case BCM6358_CPU_ID:
#endif

#ifdef CONFIG_BCM63XX_CPU_6362
		case BCM6362_CPU_ID:
#endif

#ifdef CONFIG_BCM63XX_CPU_6368
		case BCM6368_CPU_ID:
#endif
		break;
	default:
		unreachable();
	}

	return cpu_id;
}

extern u16 bcm63xx_cpu_id;

static inline u16 __pure bcm63xx_get_cpu_id(void)
{
	const u16 cpu_id = bcm63xx_cpu_id;

	return __bcm63xx_get_cpu_id(cpu_id);
}

#define BCMCPU_IS_3368()	(bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
#define BCMCPU_IS_6328()	(bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
#define BCMCPU_IS_6338()	(bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
#define BCMCPU_IS_6345()	(bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
#define BCMCPU_IS_6348()	(bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
#define BCMCPU_IS_6358()	(bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
#define BCMCPU_IS_6362()	(bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
#define BCMCPU_IS_6368()	(bcm63xx_get_cpu_id() == BCM6368_CPU_ID)

/*
 * While registers sets are (mostly) the same across 63xx CPU, base
 * address of these sets do change.
 */
enum bcm63xx_regs_set {
	RSET_DSL_LMEM = 0,
	RSET_PERF,
	RSET_TIMER,
	RSET_WDT,
	RSET_UART0,
	RSET_UART1,
	RSET_GPIO,
	RSET_SPI,
	RSET_HSSPI,
	RSET_UDC0,
	RSET_OHCI0,
	RSET_OHCI_PRIV,
	RSET_USBH_PRIV,
	RSET_USBD,
	RSET_USBDMA,
	RSET_MPI,
	RSET_PCMCIA,
	RSET_PCIE,
	RSET_DSL,
	RSET_ENET0,
	RSET_ENET1,
	RSET_ENETDMA,
	RSET_ENETDMAC,
	RSET_ENETDMAS,
	RSET_ENETSW,
	RSET_EHCI0,
	RSET_SDRAM,
	RSET_MEMC,
	RSET_DDR,
	RSET_M2M,
	RSET_ATM,
	RSET_XTM,
	RSET_XTMDMA,
	RSET_XTMDMAC,
	RSET_XTMDMAS,
	RSET_PCM,
	RSET_PCMDMA,
	RSET_PCMDMAC,
	RSET_PCMDMAS,
	RSET_RNG,
	RSET_MISC
};

#define RSET_DSL_LMEM_SIZE		(64 * 1024 * 4)
#define RSET_DSL_SIZE			4096
#define RSET_WDT_SIZE			12
#define BCM_6338_RSET_SPI_SIZE		64
#define BCM_6348_RSET_SPI_SIZE		64
#define BCM_6358_RSET_SPI_SIZE		1804
#define BCM_6368_RSET_SPI_SIZE		1804
#define RSET_ENET_SIZE			2048
#define RSET_ENETDMA_SIZE		256
#define RSET_6345_ENETDMA_SIZE		64
#define RSET_ENETDMAC_SIZE(chans)	(16 * (chans))
#define RSET_ENETDMAS_SIZE(chans)	(16 * (chans))
#define RSET_ENETSW_SIZE		65536
#define RSET_UART_SIZE			24
#define RSET_HSSPI_SIZE			1536
#define RSET_UDC_SIZE			256
#define RSET_OHCI_SIZE			256
#define RSET_EHCI_SIZE			256
#define RSET_USBD_SIZE			256
#define RSET_USBDMA_SIZE		1280
#define RSET_PCMCIA_SIZE		12
#define RSET_M2M_SIZE			256
#define RSET_ATM_SIZE			4096
#define RSET_XTM_SIZE			10240
#define RSET_XTMDMA_SIZE		256
#define RSET_XTMDMAC_SIZE(chans)	(16 * (chans))
#define RSET_XTMDMAS_SIZE(chans)	(16 * (chans))
#define RSET_RNG_SIZE			20

/*
 * 3368 register sets base address
 */
#define BCM_3368_DSL_LMEM_BASE		(0xdeadbeef)
#define BCM_3368_PERF_BASE		(0xfff8c000)
#define BCM_3368_TIMER_BASE		(0xfff8c040)
#define BCM_3368_WDT_BASE		(0xfff8c080)
#define BCM_3368_UART0_BASE		(0xfff8c100)
#define BCM_3368_UART1_BASE		(0xfff8c120)
#define BCM_3368_GPIO_BASE		(0xfff8c080)
#define BCM_3368_SPI_BASE		(0xfff8c800)
#define BCM_3368_HSSPI_BASE		(0xdeadbeef)
#define BCM_3368_UDC0_BASE		(0xdeadbeef)
#define BCM_3368_USBDMA_BASE		(0xdeadbeef)
#define BCM_3368_OHCI0_BASE		(0xdeadbeef)
#define BCM_3368_OHCI_PRIV_BASE		(0xdeadbeef)
#define BCM_3368_USBH_PRIV_BASE		(0xdeadbeef)
#define BCM_3368_USBD_BASE		(0xdeadbeef)
#define BCM_3368_MPI_BASE		(0xfff80000)
#define BCM_3368_PCMCIA_BASE		(0xfff80054)
#define BCM_3368_PCIE_BASE		(0xdeadbeef)
#define BCM_3368_SDRAM_REGS_BASE	(0xdeadbeef)
#define BCM_3368_DSL_BASE		(0xdeadbeef)
#define BCM_3368_UBUS_BASE		(0xdeadbeef)
#define BCM_3368_ENET0_BASE		(0xfff98000)
#define BCM_3368_ENET1_BASE		(0xfff98800)
#define BCM_3368_ENETDMA_BASE		(0xfff99800)
#define BCM_3368_ENETDMAC_BASE		(0xfff99900)
#define BCM_3368_ENETDMAS_BASE		(0xfff99a00)
#define BCM_3368_ENETSW_BASE		(0xdeadbeef)
#define BCM_3368_EHCI0_BASE		(0xdeadbeef)
#define BCM_3368_SDRAM_BASE		(0xdeadbeef)
#define BCM_3368_MEMC_BASE		(0xfff84000)
#define BCM_3368_DDR_BASE		(0xdeadbeef)
#define BCM_3368_M2M_BASE		(0xdeadbeef)
#define BCM_3368_ATM_BASE		(0xdeadbeef)
#define BCM_3368_XTM_BASE		(0xdeadbeef)
#define BCM_3368_XTMDMA_BASE		(0xdeadbeef)
#define BCM_3368_XTMDMAC_BASE		(0xdeadbeef)
#define BCM_3368_XTMDMAS_BASE		(0xdeadbeef)
#define BCM_3368_PCM_BASE		(0xfff9c200)
#define BCM_3368_PCMDMA_BASE		(0xdeadbeef)
#define BCM_3368_PCMDMAC_BASE		(0xdeadbeef)
#define BCM_3368_PCMDMAS_BASE		(0xdeadbeef)
#define BCM_3368_RNG_BASE		(0xdeadbeef)
#define BCM_3368_MISC_BASE		(0xdeadbeef)

/*
 * 6328 register sets base address
 */
#define BCM_6328_DSL_LMEM_BASE		(0xdeadbeef)
#define BCM_6328_PERF_BASE		(0xb0000000)
#define BCM_6328_TIMER_BASE		(0xb0000040)
#define BCM_6328_WDT_BASE		(0xb000005c)
#define BCM_6328_UART0_BASE		(0xb0000100)
#define BCM_6328_UART1_BASE		(0xb0000120)
#define BCM_6328_GPIO_BASE		(0xb0000080)
#define BCM_6328_SPI_BASE		(0xdeadbeef)
#define BCM_6328_HSSPI_BASE		(0xb0001000)
#define BCM_6328_UDC0_BASE		(0xdeadbeef)
#define BCM_6328_USBDMA_BASE		(0xb000c000)
#define BCM_6328_OHCI0_BASE		(0xb0002600)
#define BCM_6328_OHCI_PRIV_BASE		(0xdeadbeef)
#define BCM_6328_USBH_PRIV_BASE		(0xb0002700)
#define BCM_6328_USBD_BASE		(0xb0002400)
#define BCM_6328_MPI_BASE		(0xdeadbeef)
#define BCM_6328_PCMCIA_BASE		(0xdeadbeef)
#define BCM_6328_PCIE_BASE		(0xb0e40000)
#define BCM_6328_SDRAM_REGS_BASE	(0xdeadbeef)
#define BCM_6328_DSL_BASE		(0xb0001900)
#define BCM_6328_UBUS_BASE		(0xdeadbeef)
#define BCM_6328_ENET0_BASE		(0xdeadbeef)
#define BCM_6328_ENET1_BASE		(0xdeadbeef)
#define BCM_6328_ENETDMA_BASE		(0xb000d800)
#define BCM_6328_ENETDMAC_BASE		(0xb000da00)
#define BCM_6328_ENETDMAS_BASE		(0xb000dc00)
#define BCM_6328_ENETSW_BASE		(0xb0e00000)
#define BCM_6328_EHCI0_BASE		(0xb0002500)
#define BCM_6328_SDRAM_BASE		(0xdeadbeef)
#define BCM_6328_MEMC_BASE		(0xdeadbeef)
#define BCM_6328_DDR_BASE		(0xb0003000)
#define BCM_6328_M2M_BASE		(0xdeadbeef)
#define BCM_6328_ATM_BASE		(0xdeadbeef)
#define BCM_6328_XTM_BASE		(0xdeadbeef)
#define BCM_6328_XTMDMA_BASE		(0xb000b800)
#define BCM_6328_XTMDMAC_BASE		(0xdeadbeef)
#define BCM_6328_XTMDMAS_BASE		(0xdeadbeef)
#define BCM_6328_PCM_BASE		(0xb000a800)
#define BCM_6328_PCMDMA_BASE		(0xdeadbeef)
#define BCM_6328_PCMDMAC_BASE		(0xdeadbeef)
#define BCM_6328_PCMDMAS_BASE		(0xdeadbeef)
#define BCM_6328_RNG_BASE		(0xdeadbeef)
#define BCM_6328_MISC_BASE		(0xb0001800)
#define BCM_6328_OTP_BASE		(0xb0000600)

/*
 * 6338 register sets base address
 */
#define BCM_6338_DSL_LMEM_BASE		(0xfff00000)
#define BCM_6338_PERF_BASE		(0xfffe0000)
#define BCM_6338_BB_BASE		(0xfffe0100)
#define BCM_6338_TIMER_BASE		(0xfffe0200)
#define BCM_6338_WDT_BASE		(0xfffe021c)
#define BCM_6338_UART0_BASE		(0xfffe0300)
#define BCM_6338_UART1_BASE		(0xdeadbeef)
#define BCM_6338_GPIO_BASE		(0xfffe0400)
#define BCM_6338_SPI_BASE		(0xfffe0c00)
#define BCM_6338_HSSPI_BASE		(0xdeadbeef)
#define BCM_6338_UDC0_BASE		(0xdeadbeef)
#define BCM_6338_USBDMA_BASE		(0xfffe2400)
#define BCM_6338_OHCI0_BASE		(0xdeadbeef)
#define BCM_6338_OHCI_PRIV_BASE		(0xfffe3000)
#define BCM_6338_USBH_PRIV_BASE		(0xdeadbeef)
#define BCM_6338_USBD_BASE		(0xdeadbeef)
#define BCM_6338_MPI_BASE		(0xfffe3160)
#define BCM_6338_PCMCIA_BASE		(0xdeadbeef)
#define BCM_6338_PCIE_BASE		(0xdeadbeef)
#define BCM_6338_SDRAM_REGS_BASE	(0xfffe3100)
#define BCM_6338_DSL_BASE		(0xfffe1000)
#define BCM_6338_UBUS_BASE		(0xdeadbeef)
#define BCM_6338_ENET0_BASE		(0xfffe2800)
#define BCM_6338_ENET1_BASE		(0xdeadbeef)
#define BCM_6338_ENETDMA_BASE		(0xfffe2400)
#define BCM_6338_ENETDMAC_BASE		(0xfffe2500)
#define BCM_6338_ENETDMAS_BASE		(0xfffe2600)
#define BCM_6338_ENETSW_BASE		(0xdeadbeef)
#define BCM_6338_EHCI0_BASE		(0xdeadbeef)
#define BCM_6338_SDRAM_BASE		(0xfffe3100)
#define BCM_6338_MEMC_BASE		(0xdeadbeef)
#define BCM_6338_DDR_BASE		(0xdeadbeef)
#define BCM_6338_M2M_BASE		(0xdeadbeef)
#define BCM_6338_ATM_BASE		(0xfffe2000)
#define BCM_6338_XTM_BASE		(0xdeadbeef)
#define BCM_6338_XTMDMA_BASE		(0xdeadbeef)
#define BCM_6338_XTMDMAC_BASE		(0xdeadbeef)
#define BCM_6338_XTMDMAS_BASE		(0xdeadbeef)
#define BCM_6338_PCM_BASE		(0xdeadbeef)
#define BCM_6338_PCMDMA_BASE		(0xdeadbeef)
#define BCM_6338_PCMDMAC_BASE		(0xdeadbeef)
#define BCM_6338_PCMDMAS_BASE		(0xdeadbeef)
#define BCM_6338_RNG_BASE		(0xdeadbeef)
#define BCM_6338_MISC_BASE		(0xdeadbeef)

/*
 * 6345 register sets base address
 */
#define BCM_6345_DSL_LMEM_BASE		(0xfff00000)
#define BCM_6345_PERF_BASE		(0xfffe0000)
#define BCM_6345_BB_BASE		(0xfffe0100)
#define BCM_6345_TIMER_BASE		(0xfffe0200)
#define BCM_6345_WDT_BASE		(0xfffe021c)
#define BCM_6345_UART0_BASE		(0xfffe0300)
#define BCM_6345_UART1_BASE		(0xdeadbeef)
#define BCM_6345_GPIO_BASE		(0xfffe0400)
#define BCM_6345_SPI_BASE		(0xdeadbeef)
#define BCM_6345_HSSPI_BASE		(0xdeadbeef)
#define BCM_6345_UDC0_BASE		(0xdeadbeef)
#define BCM_6345_USBDMA_BASE		(0xfffe2800)
#define BCM_6345_ENET0_BASE		(0xfffe1800)
#define BCM_6345_ENETDMA_BASE		(0xfffe2800)
#define BCM_6345_ENETDMAC_BASE		(0xfffe2840)
#define BCM_6345_ENETDMAS_BASE		(0xfffe2a00)
#define BCM_6345_ENETSW_BASE		(0xdeadbeef)
#define BCM_6345_PCMCIA_BASE		(0xfffe2028)
#define BCM_6345_MPI_BASE		(0xfffe2000)
#define BCM_6345_PCIE_BASE		(0xdeadbeef)
#define BCM_6345_OHCI0_BASE		(0xfffe2100)
#define BCM_6345_OHCI_PRIV_BASE		(0xfffe2200)
#define BCM_6345_USBH_PRIV_BASE		(0xdeadbeef)
#define BCM_6345_USBD_BASE		(0xdeadbeef)
#define BCM_6345_SDRAM_REGS_BASE	(0xfffe2300)
#define BCM_6345_DSL_BASE		(0xdeadbeef)
#define BCM_6345_UBUS_BASE		(0xdeadbeef)
#define BCM_6345_ENET1_BASE		(0xdeadbeef)
#define BCM_6345_EHCI0_BASE		(0xdeadbeef)
#define BCM_6345_SDRAM_BASE		(0xfffe2300)
#define BCM_6345_MEMC_BASE		(0xdeadbeef)
#define BCM_6345_DDR_BASE		(0xdeadbeef)
#define BCM_6345_M2M_BASE		(0xdeadbeef)
#define BCM_6345_ATM_BASE		(0xfffe4000)
#define BCM_6345_XTM_BASE		(0xdeadbeef)
#define BCM_6345_XTMDMA_BASE		(0xdeadbeef)
#define BCM_6345_XTMDMAC_BASE		(0xdeadbeef)
#define BCM_6345_XTMDMAS_BASE		(0xdeadbeef)
#define BCM_6345_PCM_BASE		(0xdeadbeef)
#define BCM_6345_PCMDMA_BASE		(0xdeadbeef)
#define BCM_6345_PCMDMAC_BASE		(0xdeadbeef)
#define BCM_6345_PCMDMAS_BASE		(0xdeadbeef)
#define BCM_6345_RNG_BASE		(0xdeadbeef)
#define BCM_6345_MISC_BASE		(0xdeadbeef)

/*
 * 6348 register sets base address
 */
#define BCM_6348_DSL_LMEM_BASE		(0xfff00000)
#define BCM_6348_PERF_BASE		(0xfffe0000)
#define BCM_6348_TIMER_BASE		(0xfffe0200)
#define BCM_6348_WDT_BASE		(0xfffe021c)
#define BCM_6348_UART0_BASE		(0xfffe0300)
#define BCM_6348_UART1_BASE		(0xdeadbeef)
#define BCM_6348_GPIO_BASE		(0xfffe0400)
#define BCM_6348_SPI_BASE		(0xfffe0c00)
#define BCM_6348_HSSPI_BASE		(0xdeadbeef)
#define BCM_6348_UDC0_BASE		(0xfffe1000)
#define BCM_6348_USBDMA_BASE		(0xdeadbeef)
#define BCM_6348_OHCI0_BASE		(0xfffe1b00)
#define BCM_6348_OHCI_PRIV_BASE		(0xfffe1c00)
#define BCM_6348_USBH_PRIV_BASE		(0xdeadbeef)
#define BCM_6348_USBD_BASE		(0xdeadbeef)
#define BCM_6348_MPI_BASE		(0xfffe2000)
#define BCM_6348_PCMCIA_BASE		(0xfffe2054)
#define BCM_6348_PCIE_BASE		(0xdeadbeef)
#define BCM_6348_SDRAM_REGS_BASE	(0xfffe2300)
#define BCM_6348_M2M_BASE		(0xfffe2800)
#define BCM_6348_DSL_BASE		(0xfffe3000)
#define BCM_6348_ENET0_BASE		(0xfffe6000)
#define BCM_6348_ENET1_BASE		(0xfffe6800)
#define BCM_6348_ENETDMA_BASE		(0xfffe7000)
#define BCM_6348_ENETDMAC_BASE		(0xfffe7100)
#define BCM_6348_ENETDMAS_BASE		(0xfffe7200)
#define BCM_6348_ENETSW_BASE		(0xdeadbeef)
#define BCM_6348_EHCI0_BASE		(0xdeadbeef)
#define BCM_6348_SDRAM_BASE		(0xfffe2300)
#define BCM_6348_MEMC_BASE		(0xdeadbeef)
#define BCM_6348_DDR_BASE		(0xdeadbeef)
#define BCM_6348_ATM_BASE		(0xfffe4000)
#define BCM_6348_XTM_BASE		(0xdeadbeef)
#define BCM_6348_XTMDMA_BASE		(0xdeadbeef)
#define BCM_6348_XTMDMAC_BASE		(0xdeadbeef)
#define BCM_6348_XTMDMAS_BASE		(0xdeadbeef)
#define BCM_6348_PCM_BASE		(0xdeadbeef)
#define BCM_6348_PCMDMA_BASE		(0xdeadbeef)
#define BCM_6348_PCMDMAC_BASE		(0xdeadbeef)
#define BCM_6348_PCMDMAS_BASE		(0xdeadbeef)
#define BCM_6348_RNG_BASE		(0xdeadbeef)
#define BCM_6348_MISC_BASE		(0xdeadbeef)

/*
 * 6358 register sets base address
 */
#define BCM_6358_DSL_LMEM_BASE		(0xfff00000)
#define BCM_6358_PERF_BASE		(0xfffe0000)
#define BCM_6358_TIMER_BASE		(0xfffe0040)
#define BCM_6358_WDT_BASE		(0xfffe005c)
#define BCM_6358_UART0_BASE		(0xfffe0100)
#define BCM_6358_UART1_BASE		(0xfffe0120)
#define BCM_6358_GPIO_BASE		(0xfffe0080)
#define BCM_6358_SPI_BASE		(0xfffe0800)
#define BCM_6358_HSSPI_BASE		(0xdeadbeef)
#define BCM_6358_UDC0_BASE		(0xfffe0800)
#define BCM_6358_USBDMA_BASE		(0xdeadbeef)
#define BCM_6358_OHCI0_BASE		(0xfffe1400)
#define BCM_6358_OHCI_PRIV_BASE		(0xdeadbeef)
#define BCM_6358_USBH_PRIV_BASE		(0xfffe1500)
#define BCM_6358_USBD_BASE		(0xdeadbeef)
#define BCM_6358_MPI_BASE		(0xfffe1000)
#define BCM_6358_PCMCIA_BASE		(0xfffe1054)
#define BCM_6358_PCIE_BASE		(0xdeadbeef)
#define BCM_6358_SDRAM_REGS_BASE	(0xfffe2300)
#define BCM_6358_M2M_BASE		(0xdeadbeef)
#define BCM_6358_DSL_BASE		(0xfffe3000)
#define BCM_6358_ENET0_BASE		(0xfffe4000)
#define BCM_6358_ENET1_BASE		(0xfffe4800)
#define BCM_6358_ENETDMA_BASE		(0xfffe5000)
#define BCM_6358_ENETDMAC_BASE		(0xfffe5100)
#define BCM_6358_ENETDMAS_BASE		(0xfffe5200)
#define BCM_6358_ENETSW_BASE		(0xdeadbeef)
#define BCM_6358_EHCI0_BASE		(0xfffe1300)
#define BCM_6358_SDRAM_BASE		(0xdeadbeef)
#define BCM_6358_MEMC_BASE		(0xfffe1200)
#define BCM_6358_DDR_BASE		(0xfffe12a0)
#define BCM_6358_ATM_BASE		(0xfffe2000)
#define BCM_6358_XTM_BASE		(0xdeadbeef)
#define BCM_6358_XTMDMA_BASE		(0xdeadbeef)
#define BCM_6358_XTMDMAC_BASE		(0xdeadbeef)
#define BCM_6358_XTMDMAS_BASE		(0xdeadbeef)
#define BCM_6358_PCM_BASE		(0xfffe1600)
#define BCM_6358_PCMDMA_BASE		(0xfffe1800)
#define BCM_6358_PCMDMAC_BASE		(0xfffe1900)
#define BCM_6358_PCMDMAS_BASE		(0xfffe1a00)
#define BCM_6358_RNG_BASE		(0xdeadbeef)
#define BCM_6358_MISC_BASE		(0xdeadbeef)


/*
 * 6362 register sets base address
 */
#define BCM_6362_DSL_LMEM_BASE		(0xdeadbeef)
#define BCM_6362_PERF_BASE		(0xb0000000)
#define BCM_6362_TIMER_BASE		(0xb0000040)
#define BCM_6362_WDT_BASE		(0xb000005c)
#define BCM_6362_UART0_BASE             (0xb0000100)
#define BCM_6362_UART1_BASE		(0xb0000120)
#define BCM_6362_GPIO_BASE		(0xb0000080)
#define BCM_6362_SPI_BASE		(0xb0000800)
#define BCM_6362_HSSPI_BASE		(0xb0001000)
#define BCM_6362_UDC0_BASE		(0xdeadbeef)
#define BCM_6362_USBDMA_BASE		(0xb000c000)
#define BCM_6362_OHCI0_BASE		(0xb0002600)
#define BCM_6362_OHCI_PRIV_BASE		(0xdeadbeef)
#define BCM_6362_USBH_PRIV_BASE		(0xb0002700)
#define BCM_6362_USBD_BASE		(0xb0002400)
#define BCM_6362_MPI_BASE		(0xdeadbeef)
#define BCM_6362_PCMCIA_BASE		(0xdeadbeef)
#define BCM_6362_PCIE_BASE		(0xb0e40000)
#define BCM_6362_SDRAM_REGS_BASE	(0xdeadbeef)
#define BCM_6362_DSL_BASE		(0xdeadbeef)
#define BCM_6362_UBUS_BASE		(0xdeadbeef)
#define BCM_6362_ENET0_BASE		(0xdeadbeef)
#define BCM_6362_ENET1_BASE		(0xdeadbeef)
#define BCM_6362_ENETDMA_BASE		(0xb000d800)
#define BCM_6362_ENETDMAC_BASE		(0xb000da00)
#define BCM_6362_ENETDMAS_BASE		(0xb000dc00)
#define BCM_6362_ENETSW_BASE		(0xb0e00000)
#define BCM_6362_EHCI0_BASE		(0xb0002500)
#define BCM_6362_SDRAM_BASE		(0xdeadbeef)
#define BCM_6362_MEMC_BASE		(0xdeadbeef)
#define BCM_6362_DDR_BASE		(0xb0003000)
#define BCM_6362_M2M_BASE		(0xdeadbeef)
#define BCM_6362_ATM_BASE		(0xdeadbeef)
#define BCM_6362_XTM_BASE		(0xb0007800)
#define BCM_6362_XTMDMA_BASE		(0xb000b800)
#define BCM_6362_XTMDMAC_BASE		(0xdeadbeef)
#define BCM_6362_XTMDMAS_BASE		(0xdeadbeef)
#define BCM_6362_PCM_BASE		(0xb000a800)
#define BCM_6362_PCMDMA_BASE		(0xdeadbeef)
#define BCM_6362_PCMDMAC_BASE		(0xdeadbeef)
#define BCM_6362_PCMDMAS_BASE		(0xdeadbeef)
#define BCM_6362_RNG_BASE		(0xdeadbeef)
#define BCM_6362_MISC_BASE		(0xb0001800)

#define BCM_6362_NAND_REG_BASE		(0xb0000200)
#define BCM_6362_NAND_CACHE_BASE	(0xb0000600)
#define BCM_6362_LED_BASE		(0xb0001900)
#define BCM_6362_IPSEC_BASE		(0xb0002800)
#define BCM_6362_IPSEC_DMA_BASE		(0xb000d000)
#define BCM_6362_WLAN_CHIPCOMMON_BASE	(0xb0004000)
#define BCM_6362_WLAN_D11_BASE		(0xb0005000)
#define BCM_6362_WLAN_SHIM_BASE		(0xb0007000)

/*
 * 6368 register sets base address
 */
#define BCM_6368_DSL_LMEM_BASE		(0xdeadbeef)
#define BCM_6368_PERF_BASE		(0xb0000000)
#define BCM_6368_TIMER_BASE		(0xb0000040)
#define BCM_6368_WDT_BASE		(0xb000005c)
#define BCM_6368_UART0_BASE		(0xb0000100)
#define BCM_6368_UART1_BASE		(0xb0000120)
#define BCM_6368_GPIO_BASE		(0xb0000080)
#define BCM_6368_SPI_BASE		(0xb0000800)
#define BCM_6368_HSSPI_BASE		(0xdeadbeef)
#define BCM_6368_UDC0_BASE		(0xdeadbeef)
#define BCM_6368_USBDMA_BASE		(0xb0004800)
#define BCM_6368_OHCI0_BASE		(0xb0001600)
#define BCM_6368_OHCI_PRIV_BASE		(0xdeadbeef)
#define BCM_6368_USBH_PRIV_BASE		(0xb0001700)
#define BCM_6368_USBD_BASE		(0xb0001400)
#define BCM_6368_MPI_BASE		(0xb0001000)
#define BCM_6368_PCMCIA_BASE		(0xb0001054)
#define BCM_6368_PCIE_BASE		(0xdeadbeef)
#define BCM_6368_SDRAM_REGS_BASE	(0xdeadbeef)
#define BCM_6368_M2M_BASE		(0xdeadbeef)
#define BCM_6368_DSL_BASE		(0xdeadbeef)
#define BCM_6368_ENET0_BASE		(0xdeadbeef)
#define BCM_6368_ENET1_BASE		(0xdeadbeef)
#define BCM_6368_ENETDMA_BASE		(0xb0006800)
#define BCM_6368_ENETDMAC_BASE		(0xb0006a00)
#define BCM_6368_ENETDMAS_BASE		(0xb0006c00)
#define BCM_6368_ENETSW_BASE		(0xb0f00000)
#define BCM_6368_EHCI0_BASE		(0xb0001500)
#define BCM_6368_SDRAM_BASE		(0xdeadbeef)
#define BCM_6368_MEMC_BASE		(0xb0001200)
#define BCM_6368_DDR_BASE		(0xb0001280)
#define BCM_6368_ATM_BASE		(0xdeadbeef)
#define BCM_6368_XTM_BASE		(0xb0001800)
#define BCM_6368_XTMDMA_BASE		(0xb0005000)
#define BCM_6368_XTMDMAC_BASE		(0xb0005200)
#define BCM_6368_XTMDMAS_BASE		(0xb0005400)
#define BCM_6368_PCM_BASE		(0xb0004000)
#define BCM_6368_PCMDMA_BASE		(0xb0005800)
#define BCM_6368_PCMDMAC_BASE		(0xb0005a00)
#define BCM_6368_PCMDMAS_BASE		(0xb0005c00)
#define BCM_6368_RNG_BASE		(0xb0004180)
#define BCM_6368_MISC_BASE		(0xdeadbeef)


extern const unsigned long *bcm63xx_regs_base;

#define __GEN_CPU_REGS_TABLE(__cpu)					\
	[RSET_DSL_LMEM]		= BCM_## __cpu ##_DSL_LMEM_BASE,	\
	[RSET_PERF]		= BCM_## __cpu ##_PERF_BASE,		\
	[RSET_TIMER]		= BCM_## __cpu ##_TIMER_BASE,		\
	[RSET_WDT]		= BCM_## __cpu ##_WDT_BASE,		\
	[RSET_UART0]		= BCM_## __cpu ##_UART0_BASE,		\
	[RSET_UART1]		= BCM_## __cpu ##_UART1_BASE,		\
	[RSET_GPIO]		= BCM_## __cpu ##_GPIO_BASE,		\
	[RSET_SPI]		= BCM_## __cpu ##_SPI_BASE,		\
	[RSET_HSSPI]		= BCM_## __cpu ##_HSSPI_BASE,		\
	[RSET_UDC0]		= BCM_## __cpu ##_UDC0_BASE,		\
	[RSET_OHCI0]		= BCM_## __cpu ##_OHCI0_BASE,		\
	[RSET_OHCI_PRIV]	= BCM_## __cpu ##_OHCI_PRIV_BASE,	\
	[RSET_USBH_PRIV]	= BCM_## __cpu ##_USBH_PRIV_BASE,	\
	[RSET_USBD]		= BCM_## __cpu ##_USBD_BASE,		\
	[RSET_USBDMA]		= BCM_## __cpu ##_USBDMA_BASE,		\
	[RSET_MPI]		= BCM_## __cpu ##_MPI_BASE,		\
	[RSET_PCMCIA]		= BCM_## __cpu ##_PCMCIA_BASE,		\
	[RSET_PCIE]		= BCM_## __cpu ##_PCIE_BASE,		\
	[RSET_DSL]		= BCM_## __cpu ##_DSL_BASE,		\
	[RSET_ENET0]		= BCM_## __cpu ##_ENET0_BASE,		\
	[RSET_ENET1]		= BCM_## __cpu ##_ENET1_BASE,		\
	[RSET_ENETDMA]		= BCM_## __cpu ##_ENETDMA_BASE,		\
	[RSET_ENETDMAC]		= BCM_## __cpu ##_ENETDMAC_BASE,	\
	[RSET_ENETDMAS]		= BCM_## __cpu ##_ENETDMAS_BASE,	\
	[RSET_ENETSW]		= BCM_## __cpu ##_ENETSW_BASE,		\
	[RSET_EHCI0]		= BCM_## __cpu ##_EHCI0_BASE,		\
	[RSET_SDRAM]		= BCM_## __cpu ##_SDRAM_BASE,		\
	[RSET_MEMC]		= BCM_## __cpu ##_MEMC_BASE,		\
	[RSET_DDR]		= BCM_## __cpu ##_DDR_BASE,		\
	[RSET_M2M]		= BCM_## __cpu ##_M2M_BASE,		\
	[RSET_ATM]		= BCM_## __cpu ##_ATM_BASE,		\
	[RSET_XTM]		= BCM_## __cpu ##_XTM_BASE,		\
	[RSET_XTMDMA]		= BCM_## __cpu ##_XTMDMA_BASE,		\
	[RSET_XTMDMAC]		= BCM_## __cpu ##_XTMDMAC_BASE,		\
	[RSET_XTMDMAS]		= BCM_## __cpu ##_XTMDMAS_BASE,		\
	[RSET_PCM]		= BCM_## __cpu ##_PCM_BASE,		\
	[RSET_PCMDMA]		= BCM_## __cpu ##_PCMDMA_BASE,		\
	[RSET_PCMDMAC]		= BCM_## __cpu ##_PCMDMAC_BASE,		\
	[RSET_PCMDMAS]		= BCM_## __cpu ##_PCMDMAS_BASE,		\
	[RSET_RNG]		= BCM_## __cpu ##_RNG_BASE,		\
	[RSET_MISC]		= BCM_## __cpu ##_MISC_BASE,		\


static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
{
	return bcm63xx_regs_base[set];
}

/*
 * IRQ number changes across CPU too
 */
enum bcm63xx_irq {
	IRQ_TIMER = 0,
	IRQ_SPI,
	IRQ_UART0,
	IRQ_UART1,
	IRQ_DSL,
	IRQ_ENET0,
	IRQ_ENET1,
	IRQ_ENET_PHY,
	IRQ_HSSPI,
	IRQ_OHCI0,
	IRQ_EHCI0,
	IRQ_USBD,
	IRQ_USBD_RXDMA0,
	IRQ_USBD_TXDMA0,
	IRQ_USBD_RXDMA1,
	IRQ_USBD_TXDMA1,
	IRQ_USBD_RXDMA2,
	IRQ_USBD_TXDMA2,
	IRQ_ENET0_RXDMA,
	IRQ_ENET0_TXDMA,
	IRQ_ENET1_RXDMA,
	IRQ_ENET1_TXDMA,
	IRQ_PCI,
	IRQ_PCMCIA,
	IRQ_ATM,
	IRQ_ENETSW_RXDMA0,
	IRQ_ENETSW_RXDMA1,
	IRQ_ENETSW_RXDMA2,
	IRQ_ENETSW_RXDMA3,
	IRQ_ENETSW_TXDMA0,
	IRQ_ENETSW_TXDMA1,
	IRQ_ENETSW_TXDMA2,
	IRQ_ENETSW_TXDMA3,
	IRQ_XTM,
	IRQ_XTM_DMA0,
};

/*
 * 3368 irqs
 */
#define BCM_3368_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
#define BCM_3368_SPI_IRQ		(IRQ_INTERNAL_BASE + 1)
#define BCM_3368_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
#define BCM_3368_UART1_IRQ		(IRQ_INTERNAL_BASE + 3)
#define BCM_3368_DSL_IRQ		0
#define BCM_3368_UDC0_IRQ		0
#define BCM_3368_OHCI0_IRQ		0
#define BCM_3368_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
#define BCM_3368_ENET1_IRQ		(IRQ_INTERNAL_BASE + 6)
#define BCM_3368_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
#define BCM_3368_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
#define BCM_3368_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 16)
#define BCM_3368_HSSPI_IRQ		0
#define BCM_3368_EHCI0_IRQ		0
#define BCM_3368_USBD_IRQ		0
#define BCM_3368_USBD_RXDMA0_IRQ	0
#define BCM_3368_USBD_TXDMA0_IRQ	0
#define BCM_3368_USBD_RXDMA1_IRQ	0
#define BCM_3368_USBD_TXDMA1_IRQ	0
#define BCM_3368_USBD_RXDMA2_IRQ	0
#define BCM_3368_USBD_TXDMA2_IRQ	0
#define BCM_3368_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
#define BCM_3368_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
#define BCM_3368_PCI_IRQ		(IRQ_INTERNAL_BASE + 31)
#define BCM_3368_PCMCIA_IRQ		0
#define BCM_3368_ATM_IRQ		0
#define BCM_3368_ENETSW_RXDMA0_IRQ	0
#define BCM_3368_ENETSW_RXDMA1_IRQ	0
#define BCM_3368_ENETSW_RXDMA2_IRQ	0
#define BCM_3368_ENETSW_RXDMA3_IRQ	0
#define BCM_3368_ENETSW_TXDMA0_IRQ	0
#define BCM_3368_ENETSW_TXDMA1_IRQ	0
#define BCM_3368_ENETSW_TXDMA2_IRQ	0
#define BCM_3368_ENETSW_TXDMA3_IRQ	0
#define BCM_3368_XTM_IRQ		0
#define BCM_3368_XTM_DMA0_IRQ		0

#define BCM_3368_EXT_IRQ0		(IRQ_INTERNAL_BASE + 25)
#define BCM_3368_EXT_IRQ1		(IRQ_INTERNAL_BASE + 26)
#define BCM_3368_EXT_IRQ2		(IRQ_INTERNAL_BASE + 27)
#define BCM_3368_EXT_IRQ3		(IRQ_INTERNAL_BASE + 28)


/*
 * 6328 irqs
 */
#define BCM_6328_HIGH_IRQ_BASE		(IRQ_INTERNAL_BASE + 32)

#define BCM_6328_TIMER_IRQ		(IRQ_INTERNAL_BASE + 31)
#define BCM_6328_SPI_IRQ		0
#define BCM_6328_UART0_IRQ		(IRQ_INTERNAL_BASE + 28)
#define BCM_6328_UART1_IRQ		(BCM_6328_HIGH_IRQ_BASE + 7)
#define BCM_6328_DSL_IRQ		(IRQ_INTERNAL_BASE + 4)
#define BCM_6328_UDC0_IRQ		0
#define BCM_6328_ENET0_IRQ		0
#define BCM_6328_ENET1_IRQ		0
#define BCM_6328_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 12)
#define BCM_6328_HSSPI_IRQ		(IRQ_INTERNAL_BASE + 29)
#define BCM_6328_OHCI0_IRQ		(BCM_6328_HIGH_IRQ_BASE + 9)
#define BCM_6328_EHCI0_IRQ		(BCM_6328_HIGH_IRQ_BASE + 10)
#define BCM_6328_USBD_IRQ		(IRQ_INTERNAL_BASE + 4)
#define BCM_6328_USBD_RXDMA0_IRQ	(IRQ_INTERNAL_BASE + 5)
#define BCM_6328_USBD_TXDMA0_IRQ	(IRQ_INTERNAL_BASE + 6)
#define BCM_6328_USBD_RXDMA1_IRQ	(IRQ_INTERNAL_BASE + 7)
#define BCM_6328_USBD_TXDMA1_IRQ	(IRQ_INTERNAL_BASE + 8)
#define BCM_6328_USBD_RXDMA2_IRQ	(IRQ_INTERNAL_BASE + 9)
#define BCM_6328_USBD_TXDMA2_IRQ	(IRQ_INTERNAL_BASE + 10)
#define BCM_6328_PCMCIA_IRQ		0
#define BCM_6328_ENET0_RXDMA_IRQ	0
#define BCM_6328_ENET0_TXDMA_IRQ	0
#define BCM_6328_ENET1_RXDMA_IRQ	0
#define BCM_6328_ENET1_TXDMA_IRQ	0
#define BCM_6328_PCI_IRQ		(IRQ_INTERNAL_BASE + 23)
#define BCM_6328_ATM_IRQ		0
#define BCM_6328_ENETSW_RXDMA0_IRQ	(BCM_6328_HIGH_IRQ_BASE + 0)
#define BCM_6328_ENETSW_RXDMA1_IRQ	(BCM_6328_HIGH_IRQ_BASE + 1)
#define BCM_6328_ENETSW_RXDMA2_IRQ	(BCM_6328_HIGH_IRQ_BASE + 2)
#define BCM_6328_ENETSW_RXDMA3_IRQ	(BCM_6328_HIGH_IRQ_BASE + 3)
#define BCM_6328_ENETSW_TXDMA0_IRQ	0
#define BCM_6328_ENETSW_TXDMA1_IRQ	0
#define BCM_6328_ENETSW_TXDMA2_IRQ	0
#define BCM_6328_ENETSW_TXDMA3_IRQ	0
#define BCM_6328_XTM_IRQ		(BCM_6328_HIGH_IRQ_BASE + 31)
#define BCM_6328_XTM_DMA0_IRQ		(BCM_6328_HIGH_IRQ_BASE + 11)

#define BCM_6328_PCM_DMA0_IRQ		(IRQ_INTERNAL_BASE + 2)
#define BCM_6328_PCM_DMA1_IRQ		(IRQ_INTERNAL_BASE + 3)
#define BCM_6328_EXT_IRQ0		(IRQ_INTERNAL_BASE + 24)
#define BCM_6328_EXT_IRQ1		(IRQ_INTERNAL_BASE + 25)
#define BCM_6328_EXT_IRQ2		(IRQ_INTERNAL_BASE + 26)
#define BCM_6328_EXT_IRQ3		(IRQ_INTERNAL_BASE + 27)

/*
 * 6338 irqs
 */
#define BCM_6338_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
#define BCM_6338_SPI_IRQ		(IRQ_INTERNAL_BASE + 1)
#define BCM_6338_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
#define BCM_6338_UART1_IRQ		0
#define BCM_6338_DSL_IRQ		(IRQ_INTERNAL_BASE + 5)
#define BCM_6338_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
#define BCM_6338_ENET1_IRQ		0
#define BCM_6338_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
#define BCM_6338_HSSPI_IRQ		0
#define BCM_6338_OHCI0_IRQ		0
#define BCM_6338_EHCI0_IRQ		0
#define BCM_6338_USBD_IRQ		0
#define BCM_6338_USBD_RXDMA0_IRQ	0
#define BCM_6338_USBD_TXDMA0_IRQ	0
#define BCM_6338_USBD_RXDMA1_IRQ	0
#define BCM_6338_USBD_TXDMA1_IRQ	0
#define BCM_6338_USBD_RXDMA2_IRQ	0
#define BCM_6338_USBD_TXDMA2_IRQ	0
#define BCM_6338_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
#define BCM_6338_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 16)
#define BCM_6338_ENET1_RXDMA_IRQ	0
#define BCM_6338_ENET1_TXDMA_IRQ	0
#define BCM_6338_PCI_IRQ		0
#define BCM_6338_PCMCIA_IRQ		0
#define BCM_6338_ATM_IRQ		0
#define BCM_6338_ENETSW_RXDMA0_IRQ	0
#define BCM_6338_ENETSW_RXDMA1_IRQ	0
#define BCM_6338_ENETSW_RXDMA2_IRQ	0
#define BCM_6338_ENETSW_RXDMA3_IRQ	0
#define BCM_6338_ENETSW_TXDMA0_IRQ	0
#define BCM_6338_ENETSW_TXDMA1_IRQ	0
#define BCM_6338_ENETSW_TXDMA2_IRQ	0
#define BCM_6338_ENETSW_TXDMA3_IRQ	0
#define BCM_6338_XTM_IRQ		0
#define BCM_6338_XTM_DMA0_IRQ		0

/*
 * 6345 irqs
 */
#define BCM_6345_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
#define BCM_6345_SPI_IRQ		0
#define BCM_6345_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
#define BCM_6345_UART1_IRQ		0
#define BCM_6345_DSL_IRQ		(IRQ_INTERNAL_BASE + 3)
#define BCM_6345_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
#define BCM_6345_ENET1_IRQ		0
#define BCM_6345_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 12)
#define BCM_6345_HSSPI_IRQ		0
#define BCM_6345_OHCI0_IRQ		0
#define BCM_6345_EHCI0_IRQ		0
#define BCM_6345_USBD_IRQ		0
#define BCM_6345_USBD_RXDMA0_IRQ	0
#define BCM_6345_USBD_TXDMA0_IRQ	0
#define BCM_6345_USBD_RXDMA1_IRQ	0
#define BCM_6345_USBD_TXDMA1_IRQ	0
#define BCM_6345_USBD_RXDMA2_IRQ	0
#define BCM_6345_USBD_TXDMA2_IRQ	0
#define BCM_6345_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 1)
#define BCM_6345_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 2)
#define BCM_6345_ENET1_RXDMA_IRQ	0
#define BCM_6345_ENET1_TXDMA_IRQ	0
#define BCM_6345_PCI_IRQ		0
#define BCM_6345_PCMCIA_IRQ		0
#define BCM_6345_ATM_IRQ		0
#define BCM_6345_ENETSW_RXDMA0_IRQ	0
#define BCM_6345_ENETSW_RXDMA1_IRQ	0
#define BCM_6345_ENETSW_RXDMA2_IRQ	0
#define BCM_6345_ENETSW_RXDMA3_IRQ	0
#define BCM_6345_ENETSW_TXDMA0_IRQ	0
#define BCM_6345_ENETSW_TXDMA1_IRQ	0
#define BCM_6345_ENETSW_TXDMA2_IRQ	0
#define BCM_6345_ENETSW_TXDMA3_IRQ	0
#define BCM_6345_XTM_IRQ		0
#define BCM_6345_XTM_DMA0_IRQ		0

/*
 * 6348 irqs
 */
#define BCM_6348_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
#define BCM_6348_SPI_IRQ		(IRQ_INTERNAL_BASE + 1)
#define BCM_6348_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
#define BCM_6348_UART1_IRQ		0
#define BCM_6348_DSL_IRQ		(IRQ_INTERNAL_BASE + 4)
#define BCM_6348_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
#define BCM_6348_ENET1_IRQ		(IRQ_INTERNAL_BASE + 7)
#define BCM_6348_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
#define BCM_6348_HSSPI_IRQ		0
#define BCM_6348_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 12)
#define BCM_6348_EHCI0_IRQ		0
#define BCM_6348_USBD_IRQ		0
#define BCM_6348_USBD_RXDMA0_IRQ	0
#define BCM_6348_USBD_TXDMA0_IRQ	0
#define BCM_6348_USBD_RXDMA1_IRQ	0
#define BCM_6348_USBD_TXDMA1_IRQ	0
#define BCM_6348_USBD_RXDMA2_IRQ	0
#define BCM_6348_USBD_TXDMA2_IRQ	0
#define BCM_6348_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 20)
#define BCM_6348_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 21)
#define BCM_6348_ENET1_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 22)
#define BCM_6348_ENET1_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 23)
#define BCM_6348_PCI_IRQ		(IRQ_INTERNAL_BASE + 24)
#define BCM_6348_PCMCIA_IRQ		(IRQ_INTERNAL_BASE + 24)
#define BCM_6348_ATM_IRQ		(IRQ_INTERNAL_BASE + 5)
#define BCM_6348_ENETSW_RXDMA0_IRQ	0
#define BCM_6348_ENETSW_RXDMA1_IRQ	0
#define BCM_6348_ENETSW_RXDMA2_IRQ	0
#define BCM_6348_ENETSW_RXDMA3_IRQ	0
#define BCM_6348_ENETSW_TXDMA0_IRQ	0
#define BCM_6348_ENETSW_TXDMA1_IRQ	0
#define BCM_6348_ENETSW_TXDMA2_IRQ	0
#define BCM_6348_ENETSW_TXDMA3_IRQ	0
#define BCM_6348_XTM_IRQ		0
#define BCM_6348_XTM_DMA0_IRQ		0

/*
 * 6358 irqs
 */
#define BCM_6358_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
#define BCM_6358_SPI_IRQ		(IRQ_INTERNAL_BASE + 1)
#define BCM_6358_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
#define BCM_6358_UART1_IRQ		(IRQ_INTERNAL_BASE + 3)
#define BCM_6358_DSL_IRQ		(IRQ_INTERNAL_BASE + 29)
#define BCM_6358_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
#define BCM_6358_ENET1_IRQ		(IRQ_INTERNAL_BASE + 6)
#define BCM_6358_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
#define BCM_6358_HSSPI_IRQ		0
#define BCM_6358_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
#define BCM_6358_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 10)
#define BCM_6358_USBD_IRQ		0
#define BCM_6358_USBD_RXDMA0_IRQ	0
#define BCM_6358_USBD_TXDMA0_IRQ	0
#define BCM_6358_USBD_RXDMA1_IRQ	0
#define BCM_6358_USBD_TXDMA1_IRQ	0
#define BCM_6358_USBD_RXDMA2_IRQ	0
#define BCM_6358_USBD_TXDMA2_IRQ	0
#define BCM_6358_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
#define BCM_6358_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 16)
#define BCM_6358_ENET1_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 17)
#define BCM_6358_ENET1_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 18)
#define BCM_6358_PCI_IRQ		(IRQ_INTERNAL_BASE + 31)
#define BCM_6358_PCMCIA_IRQ		(IRQ_INTERNAL_BASE + 24)
#define BCM_6358_ATM_IRQ		(IRQ_INTERNAL_BASE + 19)
#define BCM_6358_ENETSW_RXDMA0_IRQ	0
#define BCM_6358_ENETSW_RXDMA1_IRQ	0
#define BCM_6358_ENETSW_RXDMA2_IRQ	0
#define BCM_6358_ENETSW_RXDMA3_IRQ	0
#define BCM_6358_ENETSW_TXDMA0_IRQ	0
#define BCM_6358_ENETSW_TXDMA1_IRQ	0
#define BCM_6358_ENETSW_TXDMA2_IRQ	0
#define BCM_6358_ENETSW_TXDMA3_IRQ	0
#define BCM_6358_XTM_IRQ		0
#define BCM_6358_XTM_DMA0_IRQ		0

#define BCM_6358_PCM_DMA0_IRQ		(IRQ_INTERNAL_BASE + 23)
#define BCM_6358_PCM_DMA1_IRQ		(IRQ_INTERNAL_BASE + 24)
#define BCM_6358_EXT_IRQ0		(IRQ_INTERNAL_BASE + 25)
#define BCM_6358_EXT_IRQ1		(IRQ_INTERNAL_BASE + 26)
#define BCM_6358_EXT_IRQ2		(IRQ_INTERNAL_BASE + 27)
#define BCM_6358_EXT_IRQ3		(IRQ_INTERNAL_BASE + 28)

/*
 * 6362 irqs
 */
#define BCM_6362_HIGH_IRQ_BASE		(IRQ_INTERNAL_BASE + 32)

#define BCM_6362_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
#define BCM_6362_SPI_IRQ		(IRQ_INTERNAL_BASE + 2)
#define BCM_6362_UART0_IRQ		(IRQ_INTERNAL_BASE + 3)
#define BCM_6362_UART1_IRQ		(IRQ_INTERNAL_BASE + 4)
#define BCM_6362_DSL_IRQ		(IRQ_INTERNAL_BASE + 28)
#define BCM_6362_UDC0_IRQ		0
#define BCM_6362_ENET0_IRQ		0
#define BCM_6362_ENET1_IRQ		0
#define BCM_6362_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 14)
#define BCM_6362_HSSPI_IRQ		(IRQ_INTERNAL_BASE + 5)
#define BCM_6362_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 9)
#define BCM_6362_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 10)
#define BCM_6362_USBD_IRQ		(IRQ_INTERNAL_BASE + 11)
#define BCM_6362_USBD_RXDMA0_IRQ	(IRQ_INTERNAL_BASE + 20)
#define BCM_6362_USBD_TXDMA0_IRQ	(IRQ_INTERNAL_BASE + 21)
#define BCM_6362_USBD_RXDMA1_IRQ	(IRQ_INTERNAL_BASE + 22)
#define BCM_6362_USBD_TXDMA1_IRQ	(IRQ_INTERNAL_BASE + 23)
#define BCM_6362_USBD_RXDMA2_IRQ	(IRQ_INTERNAL_BASE + 24)
#define BCM_6362_USBD_TXDMA2_IRQ	(IRQ_INTERNAL_BASE + 25)
#define BCM_6362_PCMCIA_IRQ		0
#define BCM_6362_ENET0_RXDMA_IRQ	0
#define BCM_6362_ENET0_TXDMA_IRQ	0
#define BCM_6362_ENET1_RXDMA_IRQ	0
#define BCM_6362_ENET1_TXDMA_IRQ	0
#define BCM_6362_PCI_IRQ		(IRQ_INTERNAL_BASE + 30)
#define BCM_6362_ATM_IRQ		0
#define BCM_6362_ENETSW_RXDMA0_IRQ	(BCM_6362_HIGH_IRQ_BASE + 0)
#define BCM_6362_ENETSW_RXDMA1_IRQ	(BCM_6362_HIGH_IRQ_BASE + 1)
#define BCM_6362_ENETSW_RXDMA2_IRQ	(BCM_6362_HIGH_IRQ_BASE + 2)
#define BCM_6362_ENETSW_RXDMA3_IRQ	(BCM_6362_HIGH_IRQ_BASE + 3)
#define BCM_6362_ENETSW_TXDMA0_IRQ	0
#define BCM_6362_ENETSW_TXDMA1_IRQ	0
#define BCM_6362_ENETSW_TXDMA2_IRQ	0
#define BCM_6362_ENETSW_TXDMA3_IRQ	0
#define BCM_6362_XTM_IRQ		0
#define BCM_6362_XTM_DMA0_IRQ		(BCM_6362_HIGH_IRQ_BASE + 12)

#define BCM_6362_RING_OSC_IRQ		(IRQ_INTERNAL_BASE + 1)
#define BCM_6362_WLAN_GPIO_IRQ		(IRQ_INTERNAL_BASE + 6)
#define BCM_6362_WLAN_IRQ		(IRQ_INTERNAL_BASE + 7)
#define BCM_6362_IPSEC_IRQ		(IRQ_INTERNAL_BASE + 8)
#define BCM_6362_NAND_IRQ		(IRQ_INTERNAL_BASE + 12)
#define BCM_6362_PCM_IRQ		(IRQ_INTERNAL_BASE + 13)
#define BCM_6362_DG_IRQ			(IRQ_INTERNAL_BASE + 15)
#define BCM_6362_EPHY_ENERGY0_IRQ	(IRQ_INTERNAL_BASE + 16)
#define BCM_6362_EPHY_ENERGY1_IRQ	(IRQ_INTERNAL_BASE + 17)
#define BCM_6362_EPHY_ENERGY2_IRQ	(IRQ_INTERNAL_BASE + 18)
#define BCM_6362_EPHY_ENERGY3_IRQ	(IRQ_INTERNAL_BASE + 19)
#define BCM_6362_IPSEC_DMA0_IRQ		(IRQ_INTERNAL_BASE + 26)
#define BCM_6362_IPSEC_DMA1_IRQ		(IRQ_INTERNAL_BASE + 27)
#define BCM_6362_FAP0_IRQ		(IRQ_INTERNAL_BASE + 29)
#define BCM_6362_PCM_DMA0_IRQ		(BCM_6362_HIGH_IRQ_BASE + 4)
#define BCM_6362_PCM_DMA1_IRQ		(BCM_6362_HIGH_IRQ_BASE + 5)
#define BCM_6362_DECT0_IRQ		(BCM_6362_HIGH_IRQ_BASE + 6)
#define BCM_6362_DECT1_IRQ		(BCM_6362_HIGH_IRQ_BASE + 7)
#define BCM_6362_EXT_IRQ0		(BCM_6362_HIGH_IRQ_BASE + 8)
#define BCM_6362_EXT_IRQ1		(BCM_6362_HIGH_IRQ_BASE + 9)
#define BCM_6362_EXT_IRQ2		(BCM_6362_HIGH_IRQ_BASE + 10)
#define BCM_6362_EXT_IRQ3		(BCM_6362_HIGH_IRQ_BASE + 11)

/*
 * 6368 irqs
 */
#define BCM_6368_HIGH_IRQ_BASE		(IRQ_INTERNAL_BASE + 32)

#define BCM_6368_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
#define BCM_6368_SPI_IRQ		(IRQ_INTERNAL_BASE + 1)
#define BCM_6368_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
#define BCM_6368_UART1_IRQ		(IRQ_INTERNAL_BASE + 3)
#define BCM_6368_DSL_IRQ		(IRQ_INTERNAL_BASE + 4)
#define BCM_6368_ENET0_IRQ		0
#define BCM_6368_ENET1_IRQ		0
#define BCM_6368_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 15)
#define BCM_6368_HSSPI_IRQ		0
#define BCM_6368_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
#define BCM_6368_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 7)
#define BCM_6368_USBD_IRQ		(IRQ_INTERNAL_BASE + 8)
#define BCM_6368_USBD_RXDMA0_IRQ	(IRQ_INTERNAL_BASE + 26)
#define BCM_6368_USBD_TXDMA0_IRQ	(IRQ_INTERNAL_BASE + 27)
#define BCM_6368_USBD_RXDMA1_IRQ	(IRQ_INTERNAL_BASE + 28)
#define BCM_6368_USBD_TXDMA1_IRQ	(IRQ_INTERNAL_BASE + 29)
#define BCM_6368_USBD_RXDMA2_IRQ	(IRQ_INTERNAL_BASE + 30)
#define BCM_6368_USBD_TXDMA2_IRQ	(IRQ_INTERNAL_BASE + 31)
#define BCM_6368_PCMCIA_IRQ		0
#define BCM_6368_ENET0_RXDMA_IRQ	0
#define BCM_6368_ENET0_TXDMA_IRQ	0
#define BCM_6368_ENET1_RXDMA_IRQ	0
#define BCM_6368_ENET1_TXDMA_IRQ	0
#define BCM_6368_PCI_IRQ		(IRQ_INTERNAL_BASE + 13)
#define BCM_6368_ATM_IRQ		0
#define BCM_6368_ENETSW_RXDMA0_IRQ	(BCM_6368_HIGH_IRQ_BASE + 0)
#define BCM_6368_ENETSW_RXDMA1_IRQ	(BCM_6368_HIGH_IRQ_BASE + 1)
#define BCM_6368_ENETSW_RXDMA2_IRQ	(BCM_6368_HIGH_IRQ_BASE + 2)
#define BCM_6368_ENETSW_RXDMA3_IRQ	(BCM_6368_HIGH_IRQ_BASE + 3)
#define BCM_6368_ENETSW_TXDMA0_IRQ	(BCM_6368_HIGH_IRQ_BASE + 4)
#define BCM_6368_ENETSW_TXDMA1_IRQ	(BCM_6368_HIGH_IRQ_BASE + 5)
#define BCM_6368_ENETSW_TXDMA2_IRQ	(BCM_6368_HIGH_IRQ_BASE + 6)
#define BCM_6368_ENETSW_TXDMA3_IRQ	(BCM_6368_HIGH_IRQ_BASE + 7)
#define BCM_6368_XTM_IRQ		(IRQ_INTERNAL_BASE + 11)
#define BCM_6368_XTM_DMA0_IRQ		(BCM_6368_HIGH_IRQ_BASE + 8)

#define BCM_6368_PCM_DMA0_IRQ		(BCM_6368_HIGH_IRQ_BASE + 30)
#define BCM_6368_PCM_DMA1_IRQ		(BCM_6368_HIGH_IRQ_BASE + 31)
#define BCM_6368_EXT_IRQ0		(IRQ_INTERNAL_BASE + 20)
#define BCM_6368_EXT_IRQ1		(IRQ_INTERNAL_BASE + 21)
#define BCM_6368_EXT_IRQ2		(IRQ_INTERNAL_BASE + 22)
#define BCM_6368_EXT_IRQ3		(IRQ_INTERNAL_BASE + 23)
#define BCM_6368_EXT_IRQ4		(IRQ_INTERNAL_BASE + 24)
#define BCM_6368_EXT_IRQ5		(IRQ_INTERNAL_BASE + 25)

extern const int *bcm63xx_irqs;

#define __GEN_CPU_IRQ_TABLE(__cpu)					\
	[IRQ_TIMER]		= BCM_## __cpu ##_TIMER_IRQ,		\
	[IRQ_SPI]		= BCM_## __cpu ##_SPI_IRQ,		\
	[IRQ_UART0]		= BCM_## __cpu ##_UART0_IRQ,		\
	[IRQ_UART1]		= BCM_## __cpu ##_UART1_IRQ,		\
	[IRQ_DSL]		= BCM_## __cpu ##_DSL_IRQ,		\
	[IRQ_ENET0]		= BCM_## __cpu ##_ENET0_IRQ,		\
	[IRQ_ENET1]		= BCM_## __cpu ##_ENET1_IRQ,		\
	[IRQ_ENET_PHY]		= BCM_## __cpu ##_ENET_PHY_IRQ,		\
	[IRQ_HSSPI]		= BCM_## __cpu ##_HSSPI_IRQ,		\
	[IRQ_OHCI0]		= BCM_## __cpu ##_OHCI0_IRQ,		\
	[IRQ_EHCI0]		= BCM_## __cpu ##_EHCI0_IRQ,		\
	[IRQ_USBD]		= BCM_## __cpu ##_USBD_IRQ,		\
	[IRQ_USBD_RXDMA0]	= BCM_## __cpu ##_USBD_RXDMA0_IRQ,	\
	[IRQ_USBD_TXDMA0]	= BCM_## __cpu ##_USBD_TXDMA0_IRQ,	\
	[IRQ_USBD_RXDMA1]	= BCM_## __cpu ##_USBD_RXDMA1_IRQ,	\
	[IRQ_USBD_TXDMA1]	= BCM_## __cpu ##_USBD_TXDMA1_IRQ,	\
	[IRQ_USBD_RXDMA2]	= BCM_## __cpu ##_USBD_RXDMA2_IRQ,	\
	[IRQ_USBD_TXDMA2]	= BCM_## __cpu ##_USBD_TXDMA2_IRQ,	\
	[IRQ_ENET0_RXDMA]	= BCM_## __cpu ##_ENET0_RXDMA_IRQ,	\
	[IRQ_ENET0_TXDMA]	= BCM_## __cpu ##_ENET0_TXDMA_IRQ,	\
	[IRQ_ENET1_RXDMA]	= BCM_## __cpu ##_ENET1_RXDMA_IRQ,	\
	[IRQ_ENET1_TXDMA]	= BCM_## __cpu ##_ENET1_TXDMA_IRQ,	\
	[IRQ_PCI]		= BCM_## __cpu ##_PCI_IRQ,		\
	[IRQ_PCMCIA]		= BCM_## __cpu ##_PCMCIA_IRQ,		\
	[IRQ_ATM]		= BCM_## __cpu ##_ATM_IRQ,		\
	[IRQ_ENETSW_RXDMA0]	= BCM_## __cpu ##_ENETSW_RXDMA0_IRQ,	\
	[IRQ_ENETSW_RXDMA1]	= BCM_## __cpu ##_ENETSW_RXDMA1_IRQ,	\
	[IRQ_ENETSW_RXDMA2]	= BCM_## __cpu ##_ENETSW_RXDMA2_IRQ,	\
	[IRQ_ENETSW_RXDMA3]	= BCM_## __cpu ##_ENETSW_RXDMA3_IRQ,	\
	[IRQ_ENETSW_TXDMA0]	= BCM_## __cpu ##_ENETSW_TXDMA0_IRQ,	\
	[IRQ_ENETSW_TXDMA1]	= BCM_## __cpu ##_ENETSW_TXDMA1_IRQ,	\
	[IRQ_ENETSW_TXDMA2]	= BCM_## __cpu ##_ENETSW_TXDMA2_IRQ,	\
	[IRQ_ENETSW_TXDMA3]	= BCM_## __cpu ##_ENETSW_TXDMA3_IRQ,	\
	[IRQ_XTM]		= BCM_## __cpu ##_XTM_IRQ,		\
	[IRQ_XTM_DMA0]		= BCM_## __cpu ##_XTM_DMA0_IRQ,		\

static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
{
	return bcm63xx_irqs[irq];
}

/*
 * return installed memory size
 */
unsigned int bcm63xx_get_memory_size(void);

void bcm63xx_machine_halt(void);

void bcm63xx_machine_reboot(void);

#endif /* !BCM63XX_CPU_H_ */

Youez - 2016 - github.com/yon3zu
LinuXploit