Reach Us +1 850 754 6199

Journal of Electrical Engineering and Electronic TechnologyISSN: 2325-9833

All submissions of the EM system will be redirected to Online Manuscript Submission System. Authors are requested to submit articles directly to Online Manuscript Submission System of respective journal.

An Alternative Modeling Methodology for Interconnects used in High-Speed CMOS Integrated Circuits

An Alternative Modeling Methodology for Interconnects used in High-Speed CMOS Integrated Circuits

In this paper, an alternative modeling methodology for on-chip interconnects used in the high-speed Systems on Chip is proposed. The methodology is developed from S-parameter measurements of on-chip microstrip lines, fabricated on a silicon substrate using a 0.35 μm Complementary Metal-Oxide-Semiconductor Technology, in order to determine effective circuit models and frequency dependent parameters used to represent the delay and losses associated with interconnection lines. An equation that allows to analytically determining the optimum number of sections for an RLC distributed equivalent model to accurately represent an interconnection line within specific frequency ranges is derived. The modeling methodology was applied to interconnection lines of several lengths, and up to 35 GHz obtaining good simulationexperiment correlations.

Special Features

Full Text

View

Track Your Manuscript

Share This Page

Media Partners

Associations