Short Communication, J Electr Eng Electron Technol Vol: 12 Issue: 4

High-Performance Block Cipher Using Flexible Architecture

A Sindhu^*

Department of Electronics Engineering, Bangalore University, Karnataka, India

*Corresponding Author: A Sindhu
Department of Electronics Engineering, Bangalore University, Karnataka, India,
Tel: 9786258150;
E-mail: Appusanthi1997@gmail.com

Received date: 22 February, 2023, Manuscript No. JEEET-23-89877;
Editor assigned date: 24 February, 2023, PreQC No. JEEET-23-89877 (PQ);
Reviewed date: 10 March, 2023, QC No JEEET-23-89877;
Revised date: 21 April, 2023, Manuscript No. JEEET-23-89877 (R);
Published date: 28 April, 2023, DOI: 10.4172/2325-9833.1000955

Citation: Sindhu A (2023) High-Performance Block Cipher Using Flexible Architecture. J Electr Eng Electron Technol 12:4.

Abstract

Keywords: Cryptographic; Simon; Speck; Delay; Block cipher

Introduction

Lightweight cryptography has been an important area of cryptographic research in recent years. Different lightweight block ciphers with various design strategies have been presented. The Advanced Encryption Standard (AES) is one of the most important and applicable block ciphers in hardware and software for low resource devices, the AES is a too expensive block cipher. Therefore, many lightweight block ciphers have been proposed to reduce the costs of hardware consumption than that of AES. Lightweight block cipher algorithms play an important role in the security for resource constrained devices, such as Radio Frequency Identification (RFID) tags, smart cards, and Wireless Sensor Network (WSN) nodes. Simon are lightweight block cipher families with 32 bits to 128 bits block size and 64 bits to 256 bits key length, which is suitable for lightweight hardware implementation such as embedded CPUs that are used in the low area cryptographic application systems [1]. The first method is based on high level synthesis to give more flexibility and to achieve suitable throughput. The second method is based on a bit serialized structure to achieve the minimum area and cost in the design. In this method, the structure only used 34 slices on spartan-3 FPGA. This implementation of Simon consumed 36 slices on a spartan-3 FPGA and 13 slices on a spartan-6 FPGA. The focus of this paper is the design and implementation of efficient VLSI structures for the Simon block ciphers. The throughput, execution time, and flexibility of these block ciphers are important factors for hardware implementations [2]. Therefore, the proposed structures are implemented based on efficient components for high throughput and versatile applications.

Description

In this subsection, we describe the proposed architectures for implementing the Speck block cipher. In this cipher the modular adder (mod 2n) is the main block which has the direct impact on Critical Path Delay (CPD) and hardware consumption. In the following, the structure of the modular adder based on a parallel prefix adder is presented [3]. The proposed structure of the Speck blocks cipher. In this design, during the first clock cycle, the start signal is set to “1” and the 2n-bit plaintext P(2n-1: 0) is applied to the structure and stored in two registers Reg 1 and stored in two registers Reg 1 and Reg 2. Then, in the second clock cycle, the start signal is set to “0” for computing the following rounds (Figure 1).

The intermediate results are stored in the same registers. Computations in each round consist of two shift operations, two bit wise XOR operations and one modular adder mod 2n. In the last step, the value of the final round key kr-1 is added to the output of the modular adder for generating the 2n-bit cipher text [4]. The key scheduling process in the Speck cipher for three cases m=2, 3, and 4 is shown in Figure, respectively. The master key is divided into key words k0 to km-1. In the first clock cycle, the Start signal is set to “1” and the words k0 to km-1 are loaded into the registers Reg 1 to Reg 4, respectively. During the second clock cycle, the start signal is set to “0.” In this mode, Reg 1 to Reg 3 are configured as shift registers and other key words k4 to kr-1are generated [5].

The intermediate results are stored in the same registers. Computations in each round consist of two shift operations, two bitwise XOR operations and one modular adder mod 2n. In the last step, the value of the final round key kr-1 is added to the output of the modular adder for generating the 2n-bit cipher text. The key scheduling process in the Speck cipher for three cases m=2, 3, and 4, respectively. The master key is divided into key words k0 to km-1. In the first clock cycle, the start signal is set to “1” and the words k0 to km-1 are loaded into the registers Reg 1 to Reg 4, respectively. During the second clock cycle, the start signal is set to “0.” In this mode, Reg 1 to Reg 3 are configured as shift registers and other key words k4 to kr-1 are generated [6].

The critical path delay in these structures is reduced compared with the CRA. The depth of the adder structures is reduced on the basis of generating the carry signals in parallel form. This property is the main advantage of these adders. The structural details of the existing bit parallel prefix adders. The sklansky adder has suitable hardware and time complexities compared with the others. Therefore, here, we use this adder for implementing the modular adder in the Speck block cipher.

Results

The results of the proposed implementations and other related works on Speck cipher are that indicates the critical path relay of the existing work and the proposed work of the Simon and Speck block cipher using flexible architecture. This is light weight block cipher to reduce the critical path delay to perform the encryption and decryption operation. It is most useful methoda.

Conclusion

The proposed structures are implemented on the proposed structures for Simon; the XOR operations are implemented on the basis of a tree structure for reducing critical path delay. In addition, we proposed flexible structures that can perform various configurations of the Simon ciphers supporting variable key and block sizes. Therefore, the flexible architectures provide versatile implementations with adaptive security level and the ability of encryption of longer messages based on variable key size and variable block size.

The implementation results show that the proposed structures have better performance in terms of critical path delay compared with other existing works. The result analysis are compared and verified by using Xilinx ISE 14.2 software tool. The future work is implemented by using Speck block cipher with add one adder to reduce the delay and power at the output side.

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