Journal of Computer Engineering & Information TechnologyISSN : 2324-9307

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Research Article, J Comput Eng Inf Technol Vol: 3 Issue: 1

Multi-form, Multi-format Digital Comparator

Dimitar S Tyanev1* and Dimitar G Genov2
1Department of Computer Science and Technologies, Technical University of Varna, Varna, Bulgaria
2Department of Automation of Manufacturing, Technical University of Varna, Varna, Bulgaria
Corresponding author : Dimitar S Tyanev
Department of Computer Science and Technologies, Technical University of Varna, Varna, Bulgaria
E-mail: [email protected]
Received: September 21, 2013 Accepted: December 24, 2013 Published: January 05, 2014
Citation: Tyanev DS, Genov DG (2014) Multi-form, Multi-format Digital Comparator. J Comput Eng Inf Technol 3:1. doi:10.4172/2324-9307.1000117

Abstract

Multi-form, Multi-format Digital Comparator

In this paper we analytically prove the possibility for synthesis of multi-form, multi-format digital comparator based on the unsigned comparison algorithm of binary numbers. The synthesized comparator is a new unique logical circuit, which is capable of comparing signed binary integers and binary fractions as well as binary-coded decimal numbers. This circuit is also capable of comparing floating-point numbers as represented in the IEEE-754 standard. The comparator is highly applicable since it integrates many different ways of representing the compared numbers by using this algorithm. It can successfully replace the traditional algorithm for comparison based on subtraction, which is used in digital processors. The comparator latency has been explored because it is necessary when the comparator is used in asynchronous control systems. The law of the latency distribution and its parameters has been defined.

Keywords: Digital comparator; Binary numbers; Binary-coded decimal numbers; Floating point numbers; IEEE-754 standard; Latency logical scheme

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