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Journal of Electrical Engineering & Electronic Technology
Editorial Board: Stephen Bayne, PhD
 Texas Tech University, USA  view all
ISSN: 2325-9833
Frequency: Quarterly
 
The Journal of Electrical Engineering & Electronic Technology (JEEET) promotes rigorous research that makes a significant contribution in advancing knowledge for technologies ranging from global positioning system to electric power generation. JEEET includes all major themes pertaining to the use of electronic equipments and electrical energy.
 
Journal of Electrical Engineering & Electronic Technology is a subscription based journal that provides a range of options to purchase our articles and also permits unlimited Internet Access to complete Journal content. It accepts research, review papers, online letters to the editors & brief comments on previously published articles or other relevant findings in SciTechnol. Articles submitted by authors are evaluated by a group of peer review experts in the field and ensures that the published articles are of high quality, reflect solid scholarship in their fields, and that the information they contain is accurate and reliable.
 
Current Issue
Editors & Editorial Board Members  
J Electr Eng Electron Technol 2013, 2:1   
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Design of Miniaturized Dual Band Microstrip Antenna Loaded With Asymmetric J Slot   Research Article
Abdullah Al Noman Ovi, Mahdy Rahman Chowdhury, Md. Rashedul Alam Zuboraj and Md. Abdul Matin
J Electr Eng Electron Technol 2013, 2:1    doi: 10.4172/2325-9833.1000105
 Preview

Design of Miniaturized Dual Band Microstrip Antenna Loaded With Asymmetric J Slot

In this paper, a novel design of miniaturized dual band microstrip antenna has been proposed with necessary theoretical discussion. The single layer probe feed antenna has only 23 mm × 23 mm patch. The antennas has dual band characteristics for 3G mobile, WLAN, Wi-Fi and various other applications. The bandwidth performance of each small antenna is quite satisfactory in S-band (2 GHz-4 GHz) range. Moreover, high directivity is a primary requirement for modern satellite based communication systems. The directivities of proposed two antennas are above 6 dB (at broadside) at both bands. The frequency ratio and frequency shift of the resonant frequency can be controlled by cutting new slits and changing slit lengths. These all are discussed here from theoretical point of view and simulation based results.

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Reducing Energy Consumption in Wireless Sensor Networks Using Hash Distribution Table   Research Article
Masoud Moradi and Arash Ahmadi
J Electr Eng Electron Technol 2013, 2:1    doi: 10.4172/2325-9833.1000106
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Reducing Energy Consumption in Wireless Sensor Networks Using Hash Distribution Table

Wireless sensor networks include many small sensor nodes. These nodes have limitations with respect to energy level, bandwidth, processing power, and memory. Because of these limitations, navigation, clustering, reduction of energy consumption, an increase of lifespan are much challenges in navigation through wireless sensor networks. This article presents a dispersed navigation protocol called “Bloom Filter”, which is based on older navigation protocols including Anita Kanavalli. Its aim is to optimize energy consumption of networks. This protocol was simulated using NS_2 and assessed. This study well with inexact and nonhomogeneous input and does not require heavy processing. This scheme uses the number of “sends” to a node instead of that node’s residual energy to determine its eligibility as a receiving node, and these results in drastic energy savings.

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An Alternative Modeling Methodology for Interconnects used in High-Speed CMOS Integrated Circuits   Research Article
Mónico Linares-Aranda, Reydezel Torres-Torres and Oscar González-Díaz
J Electr Eng Electron Technol 2013, 2:1    doi: 10.4172/2325-9833.1000107
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An Alternative Modeling Methodology for Interconnects used in High-Speed CMOS Integrated Circuits

In this paper, an alternative modeling methodology for on-chip interconnects used in the high-speed Systems on Chip is proposed. The methodology is developed from S-parameter measurements of on-chip microstrip lines, fabricated on a silicon substrate using a 0.35 μm Complementary Metal-Oxide-Semiconductor Technology, in order to determine effective circuit models and frequency dependent parameters used to represent the delay and losses associated with interconnection lines. An equation that allows to analytically determining the optimum number of sections for an RLC distributed equivalent model to accurately represent an interconnection line within specific frequency ranges is derived. The modeling methodology was applied to interconnection lines of several lengths, and up to 35 GHz obtaining good simulationexperiment correlations.

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