Reach Us +1 850 754 6199

Journal of Computer Engineering & Information TechnologyISSN : 2324-9307

All submissions of the EM system will be redirected to Online Manuscript Submission System. Authors are requested to submit articles directly to Online Manuscript Submission System of respective journal.

Research Article, J Comput Eng Inf Technol Vol: 4 Issue: 1

Completion Detection Model for a Digital Comparator

Dimitar ST*
Department of Computer Science and Technologies, Technical University of Varna, Bulgaria
Corresponding author : Dimitar S Tyanev
Department of Computer Science and Technologies, Technical University of Varna, Varna, Bulgaria
E-mail: [email protected]
Received: May 05, 2014 Accepted: April 27, 2015 Published: May 01, 2015
Citation: Tyanev DS (2015) Completion Detection Model for a Digital Comparator. J Comput Eng Inf Technol 4:124. doi:10.4172/2324-9307.1000124

Abstract

Completion Detection Model for a Digital Comparator

The process of switching in a multi-bit magnitude comparator has been analyzed as well as the latency with which the output features are formed. A critical analysis of the possible methods for logic gate latency evaluation is presented, namely dual-rail signal disjunction, Muller C-element and NULL Convention Logic (NCL). A new economical logic circuit for realization of completion detection when performing the operation comparison has been proposed in connection with the conclusions made. The synthesized logic circuit is based on the parallelism in the comparator circuit. The signal generated by the aforementioned circuit enables the comparator to function under the conditions of asynchronous control.

Keywords: Digital comparator; Delay; Completion detection model;Asynchronous control; Micro-pipeline unit

Track Your Manuscript

Share This Page