Journal of Computer Engineering & Information TechnologyISSN : 2324-9307

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Research Article, J Comput Eng Inf Technol Vol: 4 Issue: 4

VLSI Implementation of Lattice Wave Digital Filters Using Fixed Point Arithmetic for Increased Maximum Sampling Frequency

Meenakshi A 1*and Tarun KR2
1PhD Student, in ECE Division, Netaji Subhas Institute of Technology, Sector-3, Dwarka, New Delhi 110075, India
2Assistant Professor, ECE Division, Netaji Subhas Institute of Technology, Sector-3, Dwarka, New Delhi 110075, India
Corresponding author : Meenakshi A
PhD Student, in ECE Division, Netaji Subhas Institute of Technology, Sector-3, Dwarka, New Delhi 110075, India
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Received: September 30, 2015 Accepted: December 14, 2015 Published: December 21, 2015
Citation: Meenakshi A, Tarun KR (2015) VLSI Implementation of Lattice Wave Digital Filters Using Fixed Point Arithmetic for Increased Maximum Sampling Frequency. J Comput Eng Inf Technol 4:4. doi:10.4172/2324-9307.1000138

Abstract

VLSI Implementation of Lattice Wave Digital Filters Using Fixed Point Arithmetic for Increased Maximum Sampling Frequency

Low complexity and high speed are the key requirements of the digital filters. These filters can be realized using all-pass sections. In this paper, design and minimum hardware implementation of a fixed point lattice wave digital filter based on three port series adaptor is proposed. Here, the second-order all-pass sections are replaced with three port series adaptors. A design-level area optimization is done by converting constant multipliers into shifts and adds using canonical signed digit (CSD) techniques. The proposed implementation reduces the latency of the critical loop by reducing the number of components (adders and multipliers).

Keywords: VLSI design; Fixed point arithmetic; Canonical signed digit coefficient; Wave digital filters; Three port adaptor; Full adder

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