International Publisher of Science, Technology and Medicine

 
 
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Editor-in-chief: Ralph Coolidge Huntsinger, PhD
 California State University, USA  view all
ISSN: 2324-9307
Frequency: Quarterly
Impact Factor: 1.91*
 

Journal of Computer Engineering & Information Technology is a peer-reviewed scholarly journal  and aims to publish the most complete and reliable source of information on the discoveries and current developments in the mode of original articles, review articles, case reports, short communications, etc. in all major themes pertaining to advances in Computer Engineering & Information Technology and making them available online freely without any restrictions or any other subscriptions to researchers worldwide.

Journal of Computer Engineering & Information Technology focuses on the topics that include:

The Journal is using Editorial Manager System for quality in review process. Editorial Manager is an online manuscript submission, review and tracking system. Review processing is performed by the editorial board members of Journal of Computer Engineering & Information Technology or outside experts; at least two independent reviewers approval followed by editor approval is required for acceptance of any citable manuscript. Authors may submit manuscripts and track their progress through the online tracking system, hopefully to publication.
Submit Manuscript via Online Submission or send as an e-mail attachment to the Editorial Office at editor.jceit@scitechnol.com or editor.jceit@scitechnol.org

Confirmed Special Issues:

  1. Current Research Trends in Cloud Computing
  2. Current Trends in Applications for Software/Hardware Integration
 
Current Issue
A Swarm Negative Selection Algorithm for Email Spam Detection   Research Article
Ismaila Idris and Ali Selamat
J Comput Eng Inf Technol 2015, 4:1    doi: 10.4172/2324-9307.1000122
 Preview

A Swarm Negative Selection Algorithm for Email Spam Detection

The increased nature of email spam with the use of urge mailing tools prompt the need for detector generation to counter the menace of unsolocited email. Detector generation inspired by the human immune system implements particle swarm optimization (PSO) to generate detector in negative selection algorithm (NSA). Outlier detectors are unique features generated by local outlier factor (LOF). The local outlier factor is implemented as fitness function to determine the local best (Pbest) of each candidate detector. Velocity and position of particle swarm optimization is employed to support the movement and new particle position of each outlier detector. The particle swarm optimization (PSO) is implemented to improve detector generation in negative selection algorithm rather than the random generation of detectors. The model is called swarm negative selection algorithm (SNSA). The experimental result show that the proposed SNSA model performs better than the standard NSA.

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Logic Scheme for Determining the Number of Leftmost Insignificant Digits in a Bit-Set of Any Length   Research Article
Dimitar S Tyanev and Yulka P Petkova
J Comput Eng Inf Technol 2015, 4:1    doi: 10.4172/2324-9307.1000123
 Preview

Logic Scheme for Determining the Number of Leftmost Insignificant Digits in a Bit-Set of Any Length

The synthesized logic scheme is capable of determining the number of the leftmost insignificant digits of numbers, which are presented in a bit-set of any length. The content of the bitset can be interpreted in different ways – as signed magnitude, one’s complement or two’s complement number and also as fractional binary number. This allows the scheme to be used in devices working both with fixed-point and floating point. The number of leftmost insignificant digits of the number is necessary to implement the next highly productive one-clock left shift. This micro-operation has place in the algorithms of various machine operations performed in the digital processor. The suggested scheme does not depend on the length of the bit-set because of the cascade principle applied. The synthesized building unit solves the same problem and has a minimum length of 3 bits.

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Completion Detection Model for a Digital Comparator   Research Article
Dimitar ST
J Comput Eng Inf Technol 2015, 4:1    doi: 10.4172/2324-9307.1000124
 Preview

Completion Detection Model for a Digital Comparator

The process of switching in a multi-bit magnitude comparator has been analyzed as well as the latency with which the output features are formed. A critical analysis of the possible methods for logic gate latency evaluation is presented, namely dual-rail signal disjunction, Muller C-element and NULL Convention Logic (NCL). A new economical logic circuit for realization of completion detection when performing the operation comparison has been proposed in connection with the conclusions made. The synthesized logic circuit is based on the parallelism in the comparator circuit. The signal generated by the aforementioned circuit enables the comparator to function under the conditions of asynchronous control.

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Client Virtualization with Bare-Metal and Symmetric Partition Approach   Research Article
Eswar R, Ravi G and Giri M
J Comput Eng Inf Technol 2015, 4:1    doi: 10.4172/2324-9307.1000125
 Preview

Client Virtualization with Bare-Metal and Symmetric Partition Approach

Due to the advancements in cloud computing we can easily deploy many types of services. However this analysis of a service access platform from a client perspective show that maintaining and managing clients remain challenges end users. Service computing is an emerging paradigm for architect and providing the application. Symmetric partition based on baremetal client vitalization approach, reduced deployment cost, facilitates secure PC retirement.

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Major Impediments to Quick Dispensation of Justice in South Western Nigeria   Research Article
Aladesote OI, Johnson OV and Agbelusi O
J Comput Eng Inf Technol 2015, 4:1    doi: 10.4172/2324-9307.1000126
 Preview

Major Impediments to Quick Dispensation of Justice in South Western Nigeria

It has become a common refrain on the lips of most Nigerians that to seek redress in our courts for any legal injury sustained is a waste of time, because that relief may not come during a lifetime. This feeling of circumspection amongst Nigerians becomes even more germane if juxtaposed with the popular saying that justice delayed is justice denied. The paper therefore extracts variables or factors causing delay to quick dispensation of Justice in South Western part of Nigeria. Four hundred (400) questionnaires were distributed to judicial workers, judges, citizens and lawyers in various part of the Ondo, Ekiti, Osun Oyo, Ogun and Lagos States most especially the state capitals and Two hundred and Eighty - Six (286) were administered and returned. Thus, a response rate of 71.5% was achieved. A dataset was generated from the responses. Gain Ratio technique using C# Programming Language was used to extract factors or variables after which a threshold was set to actually determine variables that are highly causing delay in the dispensation of justice in South Western part of Nigeria.

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