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Hindi Journal of Computer Engineering & Information TechnologyISSN : 2324-9307
Dimitar ST Author
Subjects of specialization
Affiliation
Hardware Computer Systems, Computer organization
Department of Computer Science and Technologies, Technical University of Varna, Bulgaria
Biography
Dimitar S Tyanev is a senior lecturer in the Department of Computer Science and Technologies at Technical University of Varna, Varna, Bulgaria. His research interest are Hardware Computer Systems,Computer organization.
Publications
Research Article Subscription
Completion Detection Model for a Digital Comparator
Author(s): Dimitar ST
Completion Detection Model for a Digital Comparator
The process of switching in a multi-bit magnitude comparator has been analyzed as well as the latency with which the output features are formed. A critical analysis of the possible methods for logic gate latency evaluation is presented, namely dual-rail signal disjunction, Muller C-element and NULL Convention Logic (NCL). A new economical logic circuit for realization of completion detection when performing the operation comparison has been proposed in connection with the conclusions made. The synthesized view more»
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